专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10057017B2 Data forwarding with speculative error correction 有权
公开(公告)号：US10057017B2
公开(公告)日：2018-08-21
申请号：US15470928
申请日：2017-03-28
申请人： Mellanox Technologies TLV Ltd.
发明人： Liron Mula , Ran Ravid , Oded Wertheim , Ran Sela , Roy Kriss
IPC分类号： H03M13/00 , H04L1/16 , H04L29/08
CPC分类号： H04L1/16 , H04L1/0041 , H04L1/0045 , H04L1/0052 , H04L69/324
摘要： Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.

2. 发明申请

US20170279741A1 Optimizing buffer allocation for network flow control 审中-公开
公开(公告)号：US20170279741A1
公开(公告)日：2017-09-28
申请号：US15081969
申请日：2016-03-28
申请人： Mellanox Technologies TLV Ltd.
发明人： George Elias , Barak Gafni , Ran Ravid , Ido Bukspan , Zachy Haramaty
IPC分类号： H04L12/861 , H04L12/825 , H04L12/26
CPC分类号： H04L49/9005 , H04L43/0894 , H04L43/16 , H04L47/22 , H04L47/245 , H04L47/25 , H04L47/365
摘要： Communication apparatus includes a memory, which is configured to hold data packets, having respective packet sizes, for transmission over a data link, and a transmitter, which is configured to transmit the data packets over the data link at a bit rate determined by a wire speed of the data link. A shaper is coupled to throttle transmission of the data packets by the transmitter responsively to the respective packet sizes, whereby some of the data packets are transmitted over the data link at a transmission rate that is less than the bit rate.

3. 发明申请

US20160285776A1 PHYSICAL-LAYER SIGNALING OF FLOW CONTROL UPDATES 有权
标题翻译：流量控制更新的物理层信号
公开(公告)号：US20160285776A1
公开(公告)日：2016-09-29
申请号：US14664944
申请日：2015-03-23
申请人： Mellanox Technologies TLV Ltd.
发明人： Chen Gaist , Ran Ravid , Liron Mulla , Avner Hadash
IPC分类号： H04L12/801
CPC分类号： H04L47/35 , H04L1/00 , H04L1/0002 , H04L1/0034 , H04L1/18 , H04L47/28 , H04L47/34
摘要： A method for communication includes transmitting a sequence of outgoing data blocks from a network node over a communication link to a peer node, and receiving incoming data blocks from the peer node. A control field is added in a predefined location in each of the outgoing data blocks in the sequence by the network node. In at least a first subset of the outgoing data blocks in the sequence, the control field contains error control information, which is capable of causing the peer node to retransmit one or more of the incoming data blocks to the network node, while in at least a second subset of the outgoing data blocks in the sequence, disjoint from the first subset, the control field contains a flow control instruction, configured to cause the peer node to alter a rate of transmission of the incoming data blocks over the link.
摘要翻译：一种用于通信的方法包括：通过通信链路从网络节点向对等节点发送出站数据块序列，以及从所述对等节点接收传入数据块。控制字段由网络节点添加到序列中的每个输出数据块中的预定位置。在序列中的输出数据块的至少第一子集中，控制字段包含错误控制信息，该错误控制信息能够使对等节点向网络节点重传一个或多个输入数据块，同时至少所述序列中的所述输出数据块的第二子集与所述第一子集不相交，所述控制字段包含流控制指令，被配置为使所述对等节点改变所述输入数据块在所述链路上的传输速率。

4. 发明授权

US09673934B2 Error correction on demand 有权
公开(公告)号：US09673934B2
公开(公告)日：2017-06-06
申请号：US14870031
申请日：2015-09-30
申请人： Mellanox Technologies TLV Ltd.
发明人： Liron Mula , Ran Ravid , Oded Wertheim , Ran Sela , Roy Kriss
IPC分类号： H03M13/00 , H04L1/00 , H04L29/08
CPC分类号： H04L1/0045 , H04L1/0041 , H04L1/0053 , H04L69/324
摘要： Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.

5. 发明申请

US20170093526A1 ERROR CORRECTION ON DEMAND 有权
公开(公告)号：US20170093526A1
公开(公告)日：2017-03-30
申请号：US14870031
申请日：2015-09-30
申请人： Mellanox Technologies TLV Ltd.
发明人： Liron Mula , Ran Ravid , Oded Wertheim , Ran Sela , Roy Kriss
IPC分类号： H04L1/00 , H04L29/08
CPC分类号： H04L1/0045 , H04L1/0041 , H04L1/0053 , H04L69/324
摘要： Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.

6. 发明授权

US10205683B2 Optimizing buffer allocation for network flow control 有权
公开(公告)号：US10205683B2
公开(公告)日：2019-02-12
申请号：US15081969
申请日：2016-03-28
申请人： Mellanox Technologies TLV Ltd.
发明人： George Elias , Barak Gafni , Ran Ravid , Ido Bukspan , Zachy Haramaty
IPC分类号： H04L12/24 , H04L12/861 , H04L12/26 , H04L12/825
摘要： Communication apparatus includes a memory, which is configured to hold data packets, having respective packet sizes, for transmission over a data link, and a transmitter, which is configured to transmit the data packets over the data link at a bit rate determined by a wire speed of the data link. A shaper is coupled to throttle transmission of the data packets by the transmitter responsively to the respective packet sizes, whereby some of the data packets are transmitted over the data link at a transmission rate that is less than the bit rate.

7. 发明授权

US09876727B2 Physical-layer signaling of flow control updates 有权
公开(公告)号：US09876727B2
公开(公告)日：2018-01-23
申请号：US14664944
申请日：2015-03-23
申请人： Mellanox Technologies TLV Ltd.
发明人： Chen Gaist , Ran Ravid , Liron Mulla , Avner Hadash
IPC分类号： H04L12/801 , H04L12/835 , H04L12/841 , H04L1/00
CPC分类号： H04L47/35 , H04L1/00 , H04L1/0002 , H04L1/0034 , H04L1/18 , H04L47/28 , H04L47/34
摘要： A method for communication includes transmitting a sequence of outgoing data blocks from a network node over a communication link to a peer node, and receiving incoming data blocks from the peer node. A control field is added in a predefined location in each of the outgoing data blocks in the sequence by the network node. In at least a first subset of the outgoing data blocks in the sequence, the control field contains error control information, which is capable of causing the peer node to retransmit one or more of the incoming data blocks to the network node, while in at least a second subset of the outgoing data blocks in the sequence, disjoint from the first subset, the control field contains a flow control instruction, configured to cause the peer node to alter a rate of transmission of the incoming data blocks over the link.

8. 发明申请

US20170289066A1 FACILITATING COMMUNICATION OF DATA PACKETS USING CREDIT-BASED FLOW CONTROL 审中-公开
公开(公告)号：US20170289066A1
公开(公告)日：2017-10-05
申请号：US15086990
申请日：2016-03-31
申请人： Mellanox Technologies TLV Ltd.
发明人： Zachy Haramaty , Ran Ravid , Oded Wertheim
IPC分类号： H04L12/939 , H04L12/835 , H04L12/807 , H04L12/825
CPC分类号： H04L49/552 , H04L47/263 , H04L47/27 , H04L47/30
摘要： Apparatuses and methods are described that provide for credit based flow control in a network in which a public buffer is supported at a receiver node, where a transmitter node can control the use of the public buffer. In particular, the transmitter node determines a buffer credit value (TCRi) for each virtual lane of the transmitter node. The buffer credit value (TCRi) is negative (e.g., less than 0) in an instance in which a respective virtual lane private buffer is fully used and thus reflects a loan of credits from the public buffer. In addition, the transmitter node knows the needed buffer size per virtual lane for transmitting a packet in advance based on the round trip time (RTT) and maximum transmission unit (MTU) for the packet and is precluded from consuming more space on the public buffer than required to meet RTT.

9. 发明授权

US11157433B2 Multi-chip module rate adjustment 有权
公开(公告)号：US11157433B2
公开(公告)日：2021-10-26
申请号：US16752654
申请日：2020-01-26
申请人： MELLANOX TECHNOLOGIES TLV LTD.
发明人： Guy Lederman , Ran Ravid , Asaf Horev
IPC分类号： G06F13/40
摘要： A Multi-Chip-Module (MCM) includes an MCM substrate and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate. The DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced date and durations of the first time periods and the second time periods, are preset.

10. 发明申请

US20210232525A1 Multi-Chip Module Rate Adjustment 有权
公开(公告)号：US20210232525A1
公开(公告)日：2021-07-29
申请号：US16752654
申请日：2020-01-26
申请人： MELLANOX TECHNOLOGIES TLV LTD.
发明人： Guy Lederman , Ran Ravid , Asaf Horev
IPC分类号： G06F13/40
摘要： A Multi-Chip-Module (MCM) includes an MCM substrate and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus having a fixed data rate. The DPIC is configured to send data to the DCIC by alternating between (i) first time periods during which the DPIC sends over the bus both produced data and dummy data that together have the fixed data rate of the bus, and (ii) second time periods during which the DPIC sends over the bus only dummy data at the fixed data rate, wherein a rate of the produced date and durations of the first time periods and the second time periods, are preset.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式