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1. 发明授权

US08653877B2 Current mirror modified level shifter 有权
标题翻译：电流镜修改电平转换器
公开(公告)号：US08653877B2
公开(公告)日：2014-02-18
申请号：US13349982
申请日：2012-01-13
申请人： Che-Wei Wu , Meng-Fan Chang
发明人： Che-Wei Wu , Meng-Fan Chang
IPC分类号： H03L5/00
CPC分类号： H03K3/35613 , H03K3/356182 , H03K19/0013
摘要： A current mirror modified level shifter includes a pair of PMOS including a PMOS (MPL) and a PMOS (MPR), wherein a Vot node connected to a drain of the PMOS (MPR); a pair of NMOS including NMOS (MNL) and a NMOS (MNR), wherein sources of the PMOS (MPL) and the PMOS (MPR) are coupled to a high voltage (HV), respectively; gates of the PMOS (MPL) and the PMOS (MPR) coupled together through a Vm node which located between the gates of the PMOS (MPL) and the PMOS (MPR); and a suspended PMOS (MPM) coupled to drain of the PMOS (MPL), the Vm node being coupled to a Va node between drain of the suspend PMOS (MPM) and drain of the NMOS (MNL).
摘要翻译：电流镜修改电平移位器包括一对包括PMOS（MPL）和PMOS（MPR）的PMOS，其中连接到PMOS（MPR）的漏极的Vot节点; 包括NMOS（MNL）和NMOS（MNR）的一对NMOS，其中PMOS（MPL）和PMOS（MPR）的源极分别耦合到高电压（HV）; 通过位于PMOS（MPL）和PMOS（MPR）的栅极之间的Vm节点耦合在一起的PMOS（MPL）和PMOS（MPR）的栅极; 以及耦合到PMOS（MPL）的漏极的悬浮PMOS（MPM），Vm节点耦合到暂停PMOS（MPM）的漏极和NMOS（MNL）的漏极之间的Va节点。

2. 发明授权

US08462540B2 Static random access memory cell 有权
标题翻译：静态随机存取存储单元
公开(公告)号：US08462540B2
公开(公告)日：2013-06-11
申请号：US13284532
申请日：2011-10-28
申请人： Meng-Fan Chang , Lai-Fu Chen , Jui-Jen Wu , Hiroyuki Yamauchi
发明人： Meng-Fan Chang , Lai-Fu Chen , Jui-Jen Wu , Hiroyuki Yamauchi
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： A static random access memory cell comprising a first inverter, a second inverter, a first transistor, a second transistor, and a third transistor. The first inverter is cross-coupled with the second inverter. The first transistor is connected with a write word line, a write bit line, and a first output node of the first inverter. The second transistor is connected with a complementary write bit line, the write word line, and a second output node of the second inverter. The third transistor is connected with a read bit line, a read word line, and the first input node of the first inverter to form a read port transistor, and a read port is formed. The read port transistor has a feature of asymmetric threshold voltage, and the read bit line swing can be expanded by the decrease of clamping current or the boosted read bit line.
摘要翻译：一种静态随机存取存储单元，包括第一反相器，第二反相器，第一晶体管，第二晶体管和第三晶体管。第一个反相器与第二个反相器交叉耦合。第一晶体管与第一反相器的写字线，写位线和第一输出节点连接。第二晶体管与第二反相器的互补写位线，写字线和第二输出节点连接。第三晶体管与读位线，读字线和第一反相器的第一输入节点连接，形成读端口晶体管，形成读端口。读端口晶体管具有不对称阈值电压的特征，并且可以通过钳位电流或升压读位线的减小来扩展读位线摆幅。

3. 发明申请

US20110270555A1 PROCESS VARIATION DETECTION APPARATUS AND PROCESS VARIATION DETECTION METHOD 有权
标题翻译：过程变化检测装置和过程变化检测方法
公开(公告)号：US20110270555A1
公开(公告)日：2011-11-03
申请号：US12851547
申请日：2010-08-05
申请人： Ku-Feng Lin , Meng-Fan Chang , Shyh-Shyuan Sheu , Pei-Chia Chiang , Wen-Pin Lin , Chih-He Lin
发明人： Ku-Feng Lin , Meng-Fan Chang , Shyh-Shyuan Sheu , Pei-Chia Chiang , Wen-Pin Lin , Chih-He Lin
IPC分类号： G06F19/00 , G01R19/00
CPC分类号： G01R31/2837 , G11C13/00 , G11C29/021 , G11C29/028 , G11C2029/0409 , H01L22/34
摘要： A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.
摘要翻译：提供了一种过程变化检测装置和工艺变化检测方法。过程变化检测装置包括处理变化检测器和补偿信号发生器。过程变化检测器包括第一过程变化检测部件，第二过程变化检测部件和电流比较器。第一处理变化检测部件的通道是第一导电型，第二处理变化检测部件的通道是第二导电型，其中上述第一导电类型与第二导电类型不同。电流比较器连接到第一处理变化检测部件和第二处理变化检测部件，用于比较两个部件之间的电流差异并输出当前的比较结果。补偿信号发生器连接到过程变化检测器，并根据当前比较结果产生相应的补偿信号。

4. 发明申请

US20130107609A1 Static Random Access Memory Cell 有权
标题翻译：静态随机存取存储单元
公开(公告)号：US20130107609A1
公开(公告)日：2013-05-02
申请号：US13284532
申请日：2011-10-28
申请人： Meng-Fan Chang , Lai-Fu Chen , Jui-Jen Wu , Hiroyuki Yamauchi
发明人： Meng-Fan Chang , Lai-Fu Chen , Jui-Jen Wu , Hiroyuki Yamauchi
IPC分类号： G11C11/40
CPC分类号： G11C11/412
摘要： A static random access memory cell comprising a first inverter, a second inverter, a first transistor, a second transistor, and a third transistor. The first inverter is cross-coupled with the second inverter. The first transistor is connected with a write word line, a write bit line, and a first output node of the first inverter. The second transistor is connected with a complementary write bit line, the write word line, and a second output node of the second inverter. The third transistor is connected with a read bit line, a read word line, and the first input node of the first inverter to form a read port transistor, and a read port is formed. The read port transistor has a feature of asymmetric threshold voltage, and the read bit line swing can be expanded by the decrease of clamping current or the boosted read bit line.
摘要翻译：一种静态随机存取存储单元，包括第一反相器，第二反相器，第一晶体管，第二晶体管和第三晶体管。第一个反相器与第二个反相器交叉耦合。第一晶体管与第一反相器的写字线，写位线和第一输出节点连接。第二晶体管与第二反相器的互补写位线，写字线和第二输出节点连接。第三晶体管与读位线，读字线和第一反相器的第一输入节点连接，形成读端口晶体管，形成读端口。读端口晶体管具有不对称阈值电压的特征，并且可以通过钳位电流或升压读位线的减小来扩展读位线摆幅。

5. 发明授权

US08378716B2 Bulk-driven current-sense amplifier and operating method thereof 有权
标题翻译：体驱动电流检测放大器及其操作方法
公开(公告)号：US08378716B2
公开(公告)日：2013-02-19
申请号：US13178698
申请日：2011-07-08
申请人： Che-Wei Wu , Meng-Fan Chang , Ku-Feng Lin
发明人： Che-Wei Wu , Meng-Fan Chang , Ku-Feng Lin
IPC分类号： G01R19/00
CPC分类号： G11C7/06 , G11C7/062 , G11C13/0002 , G11C13/004 , G11C2013/0042 , G11C2013/0054
摘要： A bulk-driven current-sense amplifier and an amplifier operating method are disclosed. The bulk-driven current-sense amplifier includes a differential amplifier, a first driver, and a second driver. The first driver is coupled to the differential amplifier, and a first node is formed at a connectivity segment of the first driver. The second drive is coupled to the differential amplifier, and a second node is formed at a connectivity segment of the second driver. When a first switch of the first driver and a second switch of the second driver are turned on, the differential amplifier charges the first node and the second node. When the charging is completed, the first node and the second node respectively have a different stabilized potential according to currents separately flowing through a first memory unit of the first driver and a second memory unit of the second drive, and the differential amplifier generates a voltage.
摘要翻译：公开了体驱动电流检测放大器和放大器操作方法。体驱动电流检测放大器包括差分放大器，第一驱动器和第二驱动器。第一驱动器耦合到差分放大器，并且第一节点形成在第一驱动器的连接段处。第二驱动器耦合到差分放大器，并且第二节点形成在第二驱动器的连接段处。当第一驱动器的第一开关和第二驱动器的第二开关导通时，差分放大器对第一节点和第二节点充电。当充电完成时，第一节点和第二节点分别根据分别流过第一驱动器的第一存储器单元的电流和第二驱动器的第二存储器单元分别具有不同的稳定电位，并且差分放大器产生电压。

6. 发明授权

US08331134B2 Non-volatile static random access memory and operation method thereof 有权
标题翻译：非易失性静态随机存取存储器及其操作方法
公开(公告)号：US08331134B2
公开(公告)日：2012-12-11
申请号：US12853301
申请日：2010-08-10
申请人： Pi-Feng Chiu , Meng-Fan Chang , Ku-Feng Lin , Shyh-Shyuan Sheu
发明人： Pi-Feng Chiu , Meng-Fan Chang , Ku-Feng Lin , Shyh-Shyuan Sheu
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C14/0054 , G11C14/009
摘要： A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line.
摘要翻译：提供了包括锁存单元，第一开关，第二开关，第一非易失性存储器（NVM）和第二NVM的非易失性静态随机存取存储器（NV-SRAM）及其操作方法。第一和第二开关的第一端子分别连接到闩锁单元的第一和第二端子。第一和第二开关的第二端子分别连接到第一和第二位线。第一和第二开关的控制端子连接到字线。第一和第二NVM的第一端子分别连接到闩锁单元的第一和第二端子。第一和第二NVM的第二端子分别连接到第一和第二位线。第一和第二NVM的使能端子连接到使能线。

7. 发明授权

US08213213B2 Reference current generator for resistance type memory and method thereof 有权
标题翻译：电阻型存储器的参考电流发生器及其方法
公开(公告)号：US08213213B2
公开(公告)日：2012-07-03
申请号：US12614631
申请日：2009-11-09
申请人： Meng-Fan Chang , Ku-Feng Lin , Pi-Feng Chiu
发明人： Meng-Fan Chang , Ku-Feng Lin , Pi-Feng Chiu
IPC分类号： G11C11/00
CPC分类号： G11C7/14 , G11C5/147 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C2013/0054
摘要： A reference current generator for a resistance type memory and a method thereof is disclosed. The reference current generator comprises N parallel circuit sets. Each of the N parallel circuit sets is formed with at least one first reference element and second reference elements connected in parallel. The number of the first reference elements plus the number of the second reference elements is N. The resistance value of first reference elements (a first resistance value) is not equal to the resistance value of the second reference elements (a second resistance value). An equivalent resistance provided with a equivalent resistance value between the first and second resistance value is formed by connecting the N parallel circuit sets in series between an input terminal and output terminal. A reference current is outputted from the output terminal by applying an operation voltage to the input terminal.
摘要翻译：公开了一种用于电阻型存储器的参考电流发生器及其方法。参考电流发生器包括N个并联电路组。 N个并联电路组中的每一个形成有并联连接的至少一个第一参考元件和第二参考元件。第一参考元件的数量加上第二参考元件的数量为N.第一参考元件（第一电阻值）的电阻值不等于第二参考元件的电阻值（第二电阻值）。通过在输入端子和输出端子之间串联连接N个并联电路组来形成具有第一和第二电阻值之间的等效电阻值的等效电阻。通过对输入端施加工作电压，从输出端子输出基准电流。

8. 发明申请

US20110280073A1 NON-VOLATILE STATIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF 有权
标题翻译：非易失性静态随机访问存储器及其操作方法
公开(公告)号：US20110280073A1
公开(公告)日：2011-11-17
申请号：US12853301
申请日：2010-08-10
申请人： Pi-Feng Chiu , Meng-Fan Chang , Ku-Feng Lin , Shyh-Shyuan Sheu
发明人： Pi-Feng Chiu , Meng-Fan Chang , Ku-Feng Lin , Shyh-Shyuan Sheu
IPC分类号： G11C14/00
CPC分类号： G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C14/0054 , G11C14/009
摘要： A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line.
摘要翻译：提供了包括锁存单元，第一开关，第二开关，第一非易失性存储器（NVM）和第二NVM的非易失性静态随机存取存储器（NV-SRAM）及其操作方法。第一和第二开关的第一端子分别连接到闩锁单元的第一和第二端子。第一和第二开关的第二端子分别连接到第一和第二位线。第一和第二开关的控制端子连接到字线。第一和第二NVM的第一端子分别连接到闩锁单元的第一和第二端子。第一和第二NVM的第二端子分别连接到第一和第二位线。第一和第二NVM的使能端子连接到使能线。

9. 发明申请

US20110110140A1 REFERENCE CURRENT GENERATOR FOR RESISTANCE TYPE MEMORY AND METHOD THEREOF 有权
标题翻译：用于电阻型存储器的参考电流发生器及其方法
公开(公告)号：US20110110140A1
公开(公告)日：2011-05-12
申请号：US12614631
申请日：2009-11-09
申请人： Meng-Fan Chang , Ku-Feng Lin , Pi-Feng Chiu
发明人： Meng-Fan Chang , Ku-Feng Lin , Pi-Feng Chiu
IPC分类号： G11C11/00 , G11C7/02 , G11C5/14
CPC分类号： G11C7/14 , G11C5/147 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C2013/0054
摘要： A reference current generator for a resistance type memory and a method thereof is disclosed. The reference current generator comprises N parallel circuit sets. Each of the N parallel circuit sets is formed with at least one first reference element and second reference elements connected in parallel. The number of the first reference elements plus the number of the second reference elements is N. The resistance value of first reference elements (a first resistance value) is not equal to the resistance value of the second reference elements (a second resistance value). An equivalent resistance provided with a equivalent resistance value between the first and second resistance value is formed by connecting the N parallel circuit sets in series between an input terminal and output terminal. A reference current is outputted from the output terminal by applying an operation voltage to the input terminal.
摘要翻译：公开了一种用于电阻型存储器的参考电流发生器及其方法。参考电流发生器包括N个并联电路组。 N个并联电路组中的每一个形成有并联连接的至少一个第一参考元件和第二参考元件。第一参考元件的数量加上第二参考元件的数量为N.第一参考元件（第一电阻值）的电阻值不等于第二参考元件的电阻值（第二电阻值）。通过在输入端子和输出端子之间串联连接N个并联电路组来形成具有第一和第二电阻值之间的等效电阻值的等效电阻。通过对输入端施加工作电压，从输出端子输出基准电流。

10. 发明授权

US07839706B2 Dual mode accessing signal control apparatus and dual mode timing signal generating apparatus 有权
标题翻译：双模接入信号控制装置和双模定时信号发生装置
公开(公告)号：US07839706B2
公开(公告)日：2010-11-23
申请号：US12403860
申请日：2009-03-13
申请人： Meng-Fan Chang
发明人： Meng-Fan Chang
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/22 , G11C7/227 , G11C11/413
摘要： A dual mode accessing signal control apparatus for being used in a dummy cells set of a memory, and a dual mode timing signal generating apparatus comprising a dual mode accessing signal control apparatus are provided. The dual mode accessing signal control apparatus respectively generates a write delay signal and a read signal during the write and the read process. The memory is thereby capable of self-timing its write and the read process, and is able to generate a wordline signal with a shorter width in the write process to ensure an early start to precharging. As a result, the whole duty period of the memory can be shortened.
摘要翻译：提供了一种用于存储器的虚拟单元组的双模存取信号控制装置，以及包括双模存取信号控制装置的双模定时信号发生装置。双模存取信号控制装置在写入和读取过程期间分别产生写延迟信号和读信号。因此，存储器能够对其写入和读取过程进行自定时，并且能够在写入过程中产生具有较短宽度的字线信号，以确保早期开始预充电。结果，可以缩短记忆的整个占空比。

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