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1. 发明授权

US08392655B2 Apparatus for reducing accesses to levels of a storage hierarchy in a computing system 有权
标题翻译：用于减少对计算系统中的存储层级的访问的设备
公开(公告)号：US08392655B2
公开(公告)日：2013-03-05
申请号：US10674926
申请日：2003-09-30
申请人： Michael Claus Olsen , Frederick Douglis , Marcel-Catalin Rosu , Thomas Richard Hildner
发明人： Michael Claus Olsen , Frederick Douglis , Marcel-Catalin Rosu , Thomas Richard Hildner
IPC分类号： G06F12/00
CPC分类号： G06F1/3268 , G06F1/3221 , G06F1/3275 , Y02D10/13 , Y02D10/14 , Y02D10/154
摘要： An information processing system comprises first and second levels of a storage hierarchy, wherein accessing information in the first level consumes more energy than accessing information in the second level; and a processor for writing information to the second level of storage based on energy-conserving criteria. The energy-conserving criteria comprise a set of heuristics, including system state information and user preferences.
摘要翻译：信息处理系统包括存储分级的第一级和第二级，其中访问第一级的信息比访问第二级的信息消耗更多的能量; 以及基于节能标准将信息写入第二级存储的处理器。节能标准包括一组启发式，包括系统状态信息和用户偏好。

2. 发明授权

US08959008B2 Method for dynamically switching analyses and for dynamically switching models in circuit simulators 有权
标题翻译：用于动态切换分析和在电路模拟器中动态切换模型的方法
公开(公告)号：US08959008B2
公开(公告)日：2015-02-17
申请号：US13023559
申请日：2011-02-09
申请人： Michael Claus Olsen , Jie Deng , Terence B. Hook , Madan Mohan Naga Nutakki
发明人： Michael Claus Olsen , Jie Deng , Terence B. Hook , Madan Mohan Naga Nutakki
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： Performing a transient analysis with a compact FET model that is predominantly intended for DC analysis, such as an IDDQ leakage model, to enable toggling logic states in sequential logic circuits that cannot otherwise be examined in a DC analysis. An embodiment enables examining the DC or AC conditions of any logic state of any logic circuit in a DC or AC analysis, and additionally, it eliminates a potentially long execution time of a transient analysis with a DC model. Further solved is the present need to run two simulations and to maintain two netlists in order to overcome being unable to toggle certain logic states in the DC analysis. The invention achieves the aforementioned in a single simulation with a single netlist that calculates the DC operating circuit conditions with a model A on the fly at predetermined times or in certain logic states, during a transient analysis with a model B.
摘要翻译：使用主要用于直流分析（例如IDDQ泄漏模型）的紧凑型FET模型进行瞬态分析，以便能够在不能在DC分析中检查的顺序逻辑电路中切换逻辑状态。一个实施例能够检查DC或AC分析中任何逻辑电路的任何逻辑状态的DC或AC条件，此外，它消除了具有DC模型的瞬态分析的潜在长的执行时间。进一步的解决是目前需要运行两个模拟并且维护两个网表，以克服在DC分析中不能切换某些逻辑状态。本发明在具有单个网表的单个模拟中实现上述，在单个网表中，在模型B的瞬态分析期间，在预定时间或在某些逻辑状态下，用模型A计算直流运行电路条件。

3. 发明申请

US20120203532A1 Method for Dynamically Switching Analyses and For Dynamically Switching Models in Circuit Simulators 有权
标题翻译：用于动态切换分析和电路模拟器动态切换模型的方法
公开(公告)号：US20120203532A1
公开(公告)日：2012-08-09
申请号：US13023559
申请日：2011-02-09
申请人： Michael Claus Olsen , Jie Deng , Terence B. Hook , Madan Mohan Naga Nutakki
发明人： Michael Claus Olsen , Jie Deng , Terence B. Hook , Madan Mohan Naga Nutakki
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5036
摘要： Performing a transient analysis with a compact FET model that is predominantly intended for DC analysis, such as an IDDQ leakage model, to enable toggling logic states in sequential logic circuits that cannot otherwise be examined in a DC analysis. An embodiment enables examining the DC or AC conditions of any logic state of any logic circuit in a DC or AC analysis, and additionally, it eliminates a potentially long execution time of a transient analysis with a DC model. Further solved is the present need to run two simulations and to maintain two netlists in order to overcome being unable to toggle certain logic states in the DC analysis. The invention achieves the aforementioned in a single simulation with a single netlist that calculates the DC operating circuit conditions with a model A on the fly at predetermined times or in certain logic states, during a transient analysis with a model B.
摘要翻译：使用主要用于直流分析（例如IDDQ泄漏模型）的紧凑型FET模型进行瞬态分析，以便能够在不能在DC分析中检查的顺序逻辑电路中切换逻辑状态。一个实施例能够检查DC或AC分析中任何逻辑电路的任何逻辑状态的DC或AC条件，此外，它消除了具有DC模型的瞬态分析的潜在长的执行时间。进一步的解决是目前需要运行两个模拟，并维护两个网表，以克服在DC分析中不能切换某些逻辑状态。本发明在具有单个网表的单个模拟中实现上述，在单个网表中，在模型B的瞬态分析期间，在预定时间或在某些逻辑状态下，用模型A计算直流运行电路条件。

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