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1. 发明授权

US09092163B2 Method, integrated circuit and electronic device for compensating a timing signal based at least partly on determining a number of state transitions between a current set of data states and the next set of data states 有权
标题翻译：方法，集成电路和电子设备，用于至少部分地基于确定当前数据状态集合与下一组数据状态之间的状态转换的数量来补偿定时信号
公开(公告)号：US09092163B2
公开(公告)日：2015-07-28
申请号：US13510103
申请日：2009-11-30
申请人： Michael Priel , Leonid Fleshel , Anton Rozen
发明人： Michael Priel , Leonid Fleshel , Anton Rozen
IPC分类号： G06F1/12 , G06F13/42 , G11C7/10
CPC分类号： G06F1/12 , G11C7/1051 , G11C7/1066
摘要： A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.
摘要翻译：一种用于补偿定时信号的方法，其中至少一个数据信号的数据状态的输出被同步。该方法包括接收当前的数据状态集合和下一组数据状态，识别当前数据状态集合之间的状态转换和下一组数据状态，该组数据状态至少部分地决定了应用于定时信号的补偿量在当前数据状态集合和下一组数据状态之间识别的状态转换上，并将确定的补偿量应用于定时信号，使得补偿适用于下一组数据状态的输出。

2. 发明授权

US08598949B2 Electronic circuit and method for state retention power gating 有权
标题翻译：电子电路和状态保持电源门控方法
公开(公告)号：US08598949B2
公开(公告)日：2013-12-03
申请号：US13634730
申请日：2010-06-11
申请人： Michael Priel , Leonid Fleshel , Anton Rozen
发明人： Michael Priel , Leonid Fleshel , Anton Rozen
IPC分类号： G05F1/10
CPC分类号： H03K3/00 , H03K3/012 , H03K19/0008
摘要： A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit via the second power grid; and storing, by the SRPG state information.
摘要翻译：一种方法和电子电路，所述方法包括：向切换电路发送状态保持电源选通（SRPG）电路和向第一电源发送指示SRPG电路应以功能模式工作的控制信号; 由开关电路将第三电网耦合到第一电网; 通过第一电网，开关电路和第三电网从第一电源向SRPG电路供电; 经由第二电网从第二电源向第二电路供电; 向SRPG电路和第一电源发送指示SRPG电路在状态保持模式下工作的控制信号; 由开关电路将第三电网耦合到第二电网; 通过第二电网，开关电路和第三电网从第二电源向SRPG电路供电; 经由所述第二电网从所述第二电源向所述第二电路供电; 并通过SRPG状态信息存储。

3. 发明申请

US20120239960A1 METHOD FOR COMPENSATING A TIMING SIGNAL, AN INTEGRATED CIRCUIT AND ELECTRONIC DEVICE 有权
标题翻译：用于补偿定时信号，集成电路和电子设备的方法
公开(公告)号：US20120239960A1
公开(公告)日：2012-09-20
申请号：US13510103
申请日：2009-11-30
申请人： Michael Priel , Leonid Fleshel , Anton Rozen
发明人： Michael Priel , Leonid Fleshel , Anton Rozen
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G11C7/1051 , G11C7/1066
摘要： A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.
摘要翻译：一种用于补偿定时信号的方法，其中至少一个数据信号的数据状态的输出被同步。该方法包括：接收当前的一组数据状态和下一组数据状态，识别当前数据状态集合与下一组数据状态之间的状态转换，至少至少确定应用于定时信号的补偿量部分地基于在当前数据状态集合和下一组数据状态之间识别的状态转换，以及将确定的补偿量应用于定时信号，使得补偿适用于输出下一组数据状态。

4. 发明申请

US20120236630A1 BYPASS CAPACITOR CIRCUIT AND METHOD OF PROVIDING A BYPASS CAPACITANCE FOR AN INTEGRATED CIRCUIT DIE 有权
标题翻译：旁路电容器电路和为集成电路提供旁路电容的方法
公开(公告)号：US20120236630A1
公开(公告)日：2012-09-20
申请号：US13509922
申请日：2009-11-30
申请人： Michael Priel , Leonid Fleshel , Anton Rozen
发明人： Michael Priel , Leonid Fleshel , Anton Rozen
IPC分类号： G11C11/24 , H01L21/02 , H01L27/108
CPC分类号： H01L23/5223 , G11C2029/5002 , H01L22/14 , H01L22/22 , H01L23/49589 , H01L23/5286 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.
摘要翻译：用于集成电路（IC）的旁路电容器电路包括一个或多个电容性器件，每个电容器件布置在包括IC的管芯的密封环区域的段中。提供用于IC的旁路电容的方法包括提供包括多个芯片的半导体晶片装置，每个芯片包括IC; 在所述IC中的至少一个的密封环区域中布置一个或多个电容性装置; 切割半导体晶片器件; 在测试模式中，对于所述一个或多个电容性装置中的每一个，启用所述电容性装置，确定指示所述电容性装置的可操作性的可操作性参数值，以及将所述可操作性参数存储在存储装置中; 并且在正常操作模式中，根据具有指示对应的电容性器件的非缺陷性的相关联的可操作性参数值的一个或多个电容器件的电容，向IC提供旁路电容。

5. 发明授权

US09606064B2 Method of detecting irregular current flow in an integrated circuit device and apparatus therefor 有权
公开(公告)号：US09606064B2
公开(公告)日：2017-03-28
申请号：US14380738
申请日：2012-02-27
申请人： Anton Rozen , Leonid Fleshel , Michael Priel , Yoav Weizman
发明人： Anton Rozen , Leonid Fleshel , Michael Priel , Yoav Weizman
IPC分类号： G01N21/66 , G01R15/24 , G01R31/311
CPC分类号： G01N21/66 , G01R15/24 , G01R31/311
摘要： A method of detecting irregular high current flow within an integrated circuit (IC) device is described. The method comprises obtaining infrared (IR) emission information for the IC device, identifying at least one functional component within the IC device comprising a high current flow, based at least partly on the obtained IR emission information, obtaining IR emission information for at least one reference component within the IC device, and determining whether the high current flow of the at least one functional component comprises an irregular high current flow based at least partly on a comparison of respective IR emission information for the at least one functional component and the at least one reference component.

6. 发明授权

US09431338B2 Bypass capacitor circuit and method of providing a bypass capacitance for an integrated circuit die 有权
标题翻译：旁路电容电路和为集成电路管芯提供旁路电容的方法
公开(公告)号：US09431338B2
公开(公告)日：2016-08-30
申请号：US13509922
申请日：2009-11-30
申请人： Michael Priel , Leonid Fleshel , Anton Rozen
发明人： Michael Priel , Leonid Fleshel , Anton Rozen
IPC分类号： G11C11/24 , H01L23/522 , H01L23/528 , H01L23/58 , H01L23/495 , G11C29/50 , H01L21/66
CPC分类号： H01L23/5223 , G11C2029/5002 , H01L22/14 , H01L22/22 , H01L23/49589 , H01L23/5286 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.
摘要翻译：用于集成电路（IC）的旁路电容器电路包括一个或多个电容性器件，每个电容器件布置在包括IC的管芯的密封环区域的段中。提供用于IC的旁路电容的方法包括提供包括多个芯片的半导体晶片装置，每个芯片包括IC; 在所述IC中的至少一个的密封环区域中布置一个或多个电容性装置; 切割半导体晶片器件; 在测试模式中，对于所述一个或多个电容性装置中的每一个，启用所述电容性装置，确定指示所述电容性装置的可操作性的可操作性参数值，以及将所述可操作性参数存储在存储装置中; 并且在正常操作模式中，根据具有指示对应的电容性器件的非缺陷性的相关联的可操作性参数值的一个或多个电容器件的电容，向IC提供旁路电容。

7. 发明申请

US20140021557A1 APPARATUS FOR FORWARD WELL BIAS IN A SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：用于在半导体集成电路中进行正向漂移的装置
公开(公告)号：US20140021557A1
公开(公告)日：2014-01-23
申请号：US14008581
申请日：2011-03-30
申请人： Michael Priel , Leonid Fleshel , Anton Rozen , Dov Tzytkin
发明人： Michael Priel , Leonid Fleshel , Anton Rozen , Dov Tzytkin
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L27/0928
摘要： There is provided a semiconductor Integrated Circuit device having forward well biasing, in which at least one protection device is connected between a supply voltage and a forward well bias voltage.
摘要翻译：提供了具有正向井偏压的半导体集成电路装置，其中至少一个保护装置连接在电源电压和正向阱偏置电压之间。

8. 发明申请

US20130076421A1 ELECTRONIC CIRCUIT AND METHOD FOR STATE RETENTION POWER GATING 有权
标题翻译：电子电路和状态保持功率增益的方法
公开(公告)号：US20130076421A1
公开(公告)日：2013-03-28
申请号：US13634730
申请日：2010-06-11
申请人： Michael Priel , Leonid Fleshel , Anton Rozen
发明人： Michael Priel , Leonid Fleshel , Anton Rozen
IPC分类号： H03K3/00
CPC分类号： H03K3/00 , H03K3/012 , H03K19/0008
摘要： A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit via the second power grid; and storing, by the SRPG state information.
摘要翻译：一种方法和电子电路，所述方法包括：向切换电路发送状态保持电源选通（SRPG）电路和向第一电源发送指示SRPG电路应以功能模式工作的控制信号; 由开关电路将第三电网耦合到第一电网; 通过第一电网，开关电路和第三电网从第一电源向SRPG电路供电; 经由第二电网从第二电源向第二电路供电; 向SRPG电路和第一电源发送指示SRPG电路在状态保持模式下工作的控制信号; 由开关电路将第三电网耦合到第二电网; 通过第二电网，开关电路和第三电网从第二电源向SRPG电路供电; 经由所述第二电网从所述第二电源向所述第二电路供电; 并通过SRPG状态信息存储。

9. 发明授权

US08228080B2 Device and method for current estimation 有权
标题翻译：用于当前估计的装置和方法
公开(公告)号：US08228080B2
公开(公告)日：2012-07-24
申请号：US12509279
申请日：2009-07-24
申请人： Michael Priel , Leonid Fleshel , Anton Rozen
发明人： Michael Priel , Leonid Fleshel , Anton Rozen
IPC分类号： G01R31/02 , G05F3/02 , H01L23/58 , G06F1/26
CPC分类号： G01R19/0092
摘要： A device and a method for estimating a current; the method includes: setting an impedance of a power gating circuit to a measurement value; wherein the power gating circuit selectively provides power to a circuit of an integrated circuit; measuring, during a measurement period, an electrical parameter indicative of a current that flows through the power gating circuit; and reducing an impedance of the power gating circuit to a power provision value to reduce a voltage developed on the power gating circuit during a power provision period.
摘要翻译：一种用于估计电流的装置和方法; 该方法包括：将电源门控电路的阻抗设置为测量值; 其中所述功率门控电路选择性地向集成电路的电路提供电力; 在测量周期期间测量指示流过所述电力门控电路的电流的电参数; 并且将功率门控电路的阻抗减小到功率供应值以减小在供电周期期间在功率选通电路上产生的电压。

10. 发明授权

US07941721B2 System and a method for testing connectivity between a first device and a second device 有权
标题翻译：系统和用于测试第一设备和第二设备之间的连接性的方法
公开(公告)号：US07941721B2
公开(公告)日：2011-05-10
申请号：US12550516
申请日：2009-08-31
申请人： Michael Priel , Leonid Fleshel , Anton Rozen
发明人： Michael Priel , Leonid Fleshel , Anton Rozen
IPC分类号： G06F11/00
CPC分类号： G01R31/318538 , G01R31/318541
摘要： A device and a method for testing a connectivity between a first device and a second device, the method includes: writing, at a first frequency and in a serial manner, a first test word to a source boundary scan register; writing a content of the source boundary scan register, at a second frequency and in a parallel manner, to a target boundary scan register; wherein the second frequency is higher than the first frequency; reading the content of the target boundary scan register; wherein the source and target boundary scan registers are selected from a first boundary scan register of the first device and a second boundary scan register of the second device; and evaluating a connectivity between the first and second device in response to a relationship between the first test word and the content of the target boundary scan register.
摘要翻译：一种用于测试第一设备和第二设备之间的连接性的设备和方法，所述方法包括：以第一频率和串行方式将第一测试字写入源边界扫描寄存器; 将源边界扫描寄存器的内容以第二频率和并行方式写入目标边界扫描寄存器; 其中所述第二频率高于所述第一频率; 读取目标边界扫描寄存器的内容; 其中所述源和目标边界扫描寄存器从所述第一设备的第一边界扫描寄存器和所述第二设备的第二边界扫描寄存器中选择; 以及响应于所述第一测试字与所述目标边界扫描寄存器的内容之间的关系来评估所述第一和第二设备之间的连接性。

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