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1. 发明申请

US20170213787A1 INTERPOSER WITH BEYOND RETICLE FIELD CONDUCTOR PADS 有权
公开(公告)号：US20170213787A1
公开(公告)日：2017-07-27
申请号：US15007791
申请日：2016-01-27
申请人： Michael S. Alfano , Bryan Black , Michael Z. Su , Joseph R. Siegel , Julius E. Din , Anwar Kashem
发明人： Michael S. Alfano , Bryan Black , Michael Z. Su , Joseph R. Siegel , Julius E. Din , Anwar Kashem
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48
CPC分类号： H01L24/81 , H01L21/4846 , H01L21/486 , H01L23/147 , H01L23/49816 , H01L23/49822 , H01L23/5384 , H01L24/16 , H01L2224/16227
摘要： Various interposers and methods of manufacturing related thereto are disclosed. In one aspect, an apparatus is provided that includes an interposer that has a first side and a second side opposite the first side. The first side has a first reticle field and a second reticle field larger than the first reticle field. Plural conductor pads are positioned on the first side in the first reticle field. Plural dummy conductor pads are positioned on the first side in the second reticle field and outside the first reticle field.

2. 发明授权

US09806014B2 Interposer with beyond reticle field conductor pads 有权
公开(公告)号：US09806014B2
公开(公告)日：2017-10-31
申请号：US15007791
申请日：2016-01-27
申请人： Michael S. Alfano , Bryan Black , Michael Z. Su , Joseph R. Siegel , Julius E. Din , Anwar Kashem
发明人： Michael S. Alfano , Bryan Black , Michael Z. Su , Joseph R. Siegel , Julius E. Din , Anwar Kashem
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/498 , H01L21/48 , H01L23/00
CPC分类号： H01L24/81 , H01L21/4846 , H01L21/486 , H01L23/147 , H01L23/49816 , H01L23/49822 , H01L23/5384 , H01L24/16 , H01L2224/16227
摘要： Various interposers and methods of manufacturing related thereto are disclosed. In one aspect, an apparatus is provided that includes an interposer that has a first side and a second side opposite the first side. The first side has a first reticle field and a second reticle field larger than the first reticle field. Plural conductor pads are positioned on the first side in the first reticle field. Plural dummy conductor pads are positioned on the first side in the second reticle field and outside the first reticle field.

3. 发明申请

US20170092712A1 VIA CAPACITOR 审中-公开
公开(公告)号：US20170092712A1
公开(公告)日：2017-03-30
申请号：US14865664
申请日：2015-09-25
申请人： Joseph R. Siegel , Lawrence A. Bair , Bryan Black , Michael Su
发明人： Joseph R. Siegel , Lawrence A. Bair , Bryan Black , Michael Su
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , H01L27/11582 , H01L28/00
摘要： Various through silicon via capacitors and methods of fabricating the same are disclosed. In one aspect, an apparatus is provided that includes a semiconductor substrate with a portion doped with a first impurity type and a doped region of a second impurity type in the portion of the semiconductor substrate. The doped region is operable to function as a first capacitor plate. A first via hole is in the doped region. The first via hole has a first sidewall. A first insulating layer is on the first sidewall. The first insulating layer is operable to function as a capacitor dielectric. A first conductive via is in the first via hole. The first conductive via is operable to function as a second capacitor plate.

4. 发明申请

US20120166899A1 FAULT TOLERANT SCANNABLE GLITCH LATCH 有权
标题翻译：容错扫帚锁
公开(公告)号：US20120166899A1
公开(公告)日：2012-06-28
申请号：US12976170
申请日：2010-12-22
申请人： Kevin M. Gillespie , Joseph R. Siegel , Dwight K. Elvey , Harry R. Fair
发明人： Kevin M. Gillespie , Joseph R. Siegel , Dwight K. Elvey , Harry R. Fair
IPC分类号： G06F11/00
CPC分类号： G01R31/318541
摘要： A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is described. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been driven high due to the stuck-at zero fault.
摘要翻译：描述了一种与扫描链一起使用的容错可扫描毛刺锁，可实现机床和零件的复位，调试和修复。扫描移位使能信号控制开关，使得在扫描链操作期间，防止数据输入线上的卡入零故障驱动电压到状态节点或拉高状态节点。因此消除了卡住零故障的传播。扫描移位使能信号还控制一个开关，该开关使扫描数据和状态节点的并联路径能够由于卡住的零故障而被驱动为高电平。

5. 发明授权

US06907556B2 Scanable R-S glitch latch for dynamic circuits 有权
标题翻译：用于动态电路的可扫描R-S毛刺锁
公开(公告)号：US06907556B2
公开(公告)日：2005-06-14
申请号：US10060716
申请日：2002-01-30
申请人： Joseph R. Siegel
发明人： Joseph R. Siegel
IPC分类号： G01R31/3185 , G01R31/28 , G11C19/00
CPC分类号： G01R31/318541 , G01R31/318536
摘要： A dynamic sequential device is provided that is adapted for scan control and observation. The dynamic sequential device may be scanned in-circuit as part of a scan chain in a VLSI device or it may be scanned as a discrete device. The dynamic sequential device maintains performance with respect to speed while allowing control and observation of its internal machine states.
摘要翻译：提供了适用于扫描控制和观察的动态顺序设备。动态顺序设备可以在电路中作为VLSI设备中扫描链的一部分进行扫描，或者可以作为分立设备进行扫描。动态顺序设备保持相对于速度的性能，同时允许控制和观察其内部机器状态。

6. 发明授权

US08850278B2 Fault tolerant scannable glitch latch 有权
标题翻译：容错可扫描毛刺锁
公开(公告)号：US08850278B2
公开(公告)日：2014-09-30
申请号：US12976170
申请日：2010-12-22
申请人： Kevin M. Gillespie , Joseph R. Siegel , Dwight K. Elvey , Harry R. Fair
发明人： Kevin M. Gillespie , Joseph R. Siegel , Dwight K. Elvey , Harry R. Fair
IPC分类号： G06F11/00 , G01R31/3185
CPC分类号： G01R31/318541
摘要： A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is described. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been driven high due to the stuck-at zero fault.
摘要翻译：描述了一种与扫描链一起使用的容错可扫描毛刺锁，可实现机床和零件的复位，调试和修复。扫描移位使能信号控制开关，使得在扫描链操作期间，防止数据输入线上的卡入零故障驱动电压到状态节点或拉高状态节点。因此消除了卡住零故障的传播。扫描移位使能信号还控制一个开关，该开关使扫描数据和状态节点的并联路径能够由于卡住的零故障而被驱动为高电平。

7. 发明授权

US06720813B1 Dual edge-triggered flip-flop design with asynchronous programmable reset 有权
标题翻译：具有异步可编程复位的双边沿触发触发器设计
公开(公告)号：US06720813B1
公开(公告)日：2004-04-13
申请号：US10390286
申请日：2003-03-17
申请人： Gin S. Yee , Pradeep R. Trivedi , Joseph R. Siegel
发明人： Gin S. Yee , Pradeep R. Trivedi , Joseph R. Siegel
IPC分类号： H03K3037
CPC分类号： H03K3/037
摘要： A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge-triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge-triggered or a dual edge-triggered device. Thus, the dual edge-triggered flip-flop may be used multiple types of computing environments.
摘要翻译：提供可以独立于时钟信号可编程地复位的双边沿触发触发器。使用外部产生的复位值，双边沿触发的触发器可以异步编程以复位为逻辑高或逻辑低电平。此外，提供可以设置为多个触发模式的双边沿触发触发器。使用外部产生的使能信号，双边沿触发触发器可以被设置为单边沿触发或双边沿触发器件。因此，双边沿触发的触发器可以用于多种类型的计算环境。

8. 发明授权

US06700946B2 System and method for automatic generation of an at-speed counter 有权
标题翻译：自动生成速度计数器的系统和方法
公开(公告)号：US06700946B2
公开(公告)日：2004-03-02
申请号：US10071506
申请日：2002-02-08
申请人： Kamran Zarrineh , Kenneth House , Joseph R. Siegel
发明人： Kamran Zarrineh , Kenneth House , Joseph R. Siegel
IPC分类号： H03K2300
CPC分类号： G06F1/04 , H03K21/40
摘要： Methods and systems for automatic generation of an at-speed binary counter are described. The binary counter includes a slow counter that increments when a fast counter overflows to keep up with a fast clock. A framework to automatically generate a Hardware Description Language (HDL) for an at-speed binary counter is also described.
摘要翻译：描述了用于自动生成速度二进制计数器的方法和系统。二进制计数器包括一个慢速计数器，当快速计数器溢出以跟上快速时钟时递增。还描述了自动生成用于速度二进制计数器的硬件描述语言（HDL）的框架。

9. 发明授权

US07000164B2 Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops 有权
标题翻译：使用电平敏感锁存器和边沿触发触发器在VLSI系统中扫描测试和计时动态多米诺骨架电路的方法
公开(公告)号：US07000164B2
公开(公告)日：2006-02-14
申请号：US10060179
申请日：2002-01-30
申请人： Joseph R. Siegel , David J. Greenhill , Ban-Pak Wong
发明人： Joseph R. Siegel , David J. Greenhill , Ban-Pak Wong
IPC分类号： G01R31/28 , H04L7/00
CPC分类号： G01R31/318552 , G01R31/318594
摘要： A system and method is provided for scan control and observation of a logical circuit that does not halt the operation of the system clock. Thus, all dynamic circuits within the system continue to evaluate and precharge normally. Moreover, the traditional method of placing a multiplexer before the data input of a clocked storage element to perform scan control and observation is no longer required. Consequently, the system and method provide a more efficient manner in which to perform scan control and observation of a logical circuit.
摘要翻译：提供了一种用于扫描控制和观察不停止系统时钟的操作的逻辑电路的系统和方法。因此，系统内的所有动态电路继续正常地进行评估和预充电。此外，不再需要在时钟存储元件的数据输入之前放置多路复用器以进行扫描控制和观察的传统方法。因此，系统和方法提供了更有效的方式来执行逻辑电路的扫描控制和观察。

10. 发明授权

US06594194B2 Memory array with common word line 有权
标题翻译：具有通用字线的存储器阵列
公开(公告)号：US06594194B2
公开(公告)日：2003-07-15
申请号：US09902914
申请日：2001-07-11
申请人： Spencer M. Gold , Joseph R. Siegel
发明人： Spencer M. Gold , Joseph R. Siegel
IPC分类号： G11C800
CPC分类号： G11C11/419 , G11C8/16
摘要： The present invention provides logic to write data to a multi-ported memory array. The memory array is comprised of a plurality of memory banks and a common write word line shared by the memory banks. The memory array includes a plurality of write buffers, wherein each write buffer is associated with one of the memory banks. The memory array further comprises a selector module for selecting a write buffer to write data into its associated memory bank. The memory array further includes a writing module within the write buffer for writing data into the selected memory bank by way of a signal to the memory bank.
摘要翻译：本发明提供将数据写入多端口存储器阵列的逻辑。存储器阵列由多个存储器组和由存储器组共享的公共写入字线组成。存储器阵列包括多个写缓冲器，其中每个写缓冲器与存储体之一相关联。存储器阵列还包括选择器模块，用于选择写入缓冲器以将数据写入其相关联的存储体。存储器阵列还包括写入缓冲器内的写入模块，用于通过向存储体的信号将数据写入所选存储体。

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