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1. 发明申请

US20120193749A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120193749A1
公开(公告)日：2012-08-02
申请号：US13447566
申请日：2012-04-16
申请人： Ryouichi KAWANO , Tomoyuki Yamazaki , Michio Nemoto , Mituhiro Kakefu
发明人： Ryouichi KAWANO , Tomoyuki Yamazaki , Michio Nemoto , Mituhiro Kakefu
IPC分类号： H01L29/06
CPC分类号： H01L29/8611 , H01L29/0619 , H01L29/0692 , H01L29/404 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.
摘要翻译：在具有pn结二极管结构的半导体器件中，包括阳极扩散区域包括边缘区域，阳极扩散区域上的阳极电极和阳极扩散区域的边缘区域上的绝缘膜，阳极扩散区域上方的绝缘膜的阳极电极面积介于阳极电极和阳极扩散区之间的绝缘膜的面积比阳极扩散区边缘区域的面积窄。

2. 发明授权

US08178941B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08178941B2
公开(公告)日：2012-05-15
申请号：US12507735
申请日：2009-07-22
申请人： Ryouichi Kawano , Tomoyuki Yamazaki , Michio Nemoto , Mituhiro Kakefu
发明人： Ryouichi Kawano , Tomoyuki Yamazaki , Michio Nemoto , Mituhiro Kakefu
IPC分类号： H01L23/58
CPC分类号： H01L29/8611 , H01L29/0619 , H01L29/0692 , H01L29/404 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.
摘要翻译：在具有pn结二极管结构的半导体器件中，包括阳极扩散区域包括边缘区域，阳极扩散区域上的阳极电极和阳极扩散区域的边缘区域上的绝缘膜，阳极扩散区域上方的绝缘膜的阳极电极面积介于阳极电极和阳极扩散区之间的绝缘膜的面积比阳极扩散区边缘区域的面积窄。

3. 发明授权

US07157785B2 Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices 有权
标题翻译：半导体器件及其制造方法，以及使用半导体器件的双向开关器件
公开(公告)号：US07157785B2
公开(公告)日：2007-01-02
申请号：US10928927
申请日：2004-08-27
申请人： Manabu Takei , Tatsuya Naito , Michio Nemoto
发明人： Manabu Takei , Tatsuya Naito , Michio Nemoto
IPC分类号： H01L27/85 , H01L27/102 , H01L29/70 , H01L31/11 , H01L31/07
CPC分类号： H02M7/003 , H01L29/0696 , H01L29/7395 , H01L29/872
摘要： A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n−-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.
摘要翻译：公开了一种半导体器件，其减少由反向偏置电压施加引起的反向泄漏电流并且降低IGBT的导通电压。提供了使用半导体器件的双向开关器件，并且公开了制造半导体器件的方法。反向阻断IGBT通过将p型基极区域和发射极电极之间延伸的类型漂移区域1的部分引入肖特基接触来形成反向漏电流和导通电压，形成肖特基路口。

4. 发明授权

US08502345B2 Reverse-conducting insulated gate bipolar transistor 有权
标题翻译：反向绝缘栅双极晶体管
公开(公告)号：US08502345B2
公开(公告)日：2013-08-06
申请号：US13015229
申请日：2011-01-27
申请人： Michio Nemoto , Souichi Yoshida
发明人： Michio Nemoto , Souichi Yoshida
IPC分类号： E21B49/00
CPC分类号： H01L29/739
摘要： Reverse-conducting insulated gate bipolar transistor in which IGBT region and FWD region are integrated into a single body in a semiconductor substrate with a common active region is disclosed. MOS gate structure is on a first major surface side. Rear surface side structure is in a second major surface side of the semiconductor substrate and includes a plurality of recessed parts vertical to the second major surface, which are repeated periodically along the second major surface. A plurality of protruding parts are interposed between the recessed parts. Rear surface side structure includes p type collector region on a bottom surface of the recessed part, n type first field stop region at a position deeper than the collector region, n type cathode region on the top surface of the protruding part, and n type second field stop region in the protruding part at a position deeper than the cathode region.
摘要翻译：公开了其中IGBT区域和FWD区域在具有公共有源区域的半导体衬底中集成到单个体中的反向导通绝缘栅双极晶体管。 MOS栅结构在第一主表面上。后表面侧结构位于半导体基板的第二主表面侧，并且包括与第二主表面垂直的多个凹部，其沿着第二主表面周期性重复。在凹部之间插入有多个突出部。后表面侧结构包括凹部的底面上的p型集电极区域，位于比集电极区域深的位置的n型第一场停止区域，突出部分的顶面上的n型阴极区域和n型第二区域位于比阴极区域更深的位置处的突出部中的场停止区域。

5. 发明授权

US08163630B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08163630B2
公开(公告)日：2012-04-24
申请号：US12662349
申请日：2010-04-13
申请人： Michio Nemoto
发明人： Michio Nemoto
IPC分类号： H01L21/268
CPC分类号： H01L29/861 , H01L29/36 , H01L29/66136 , H01L29/868
摘要： A method of manufacturing a semiconductor device by thinning a substrate by grinding, and performing ion implantation. In a diode in which a P anode layer and an anode electrode are formed at a side of a right face of an N− drift layer, and an N+ cathode layer and a cathode electrode are formed at a side of a back face of the N− drift layer, an N cathode buffer layer is formed thick compared with the N+-type cathode layer between the N−-type drift layer and the N+ cathode layer, the buffer layer being high in concentration compared with the N− drift layer, and low compared with the N+ cathode layer. When a reverse bias voltage is applied, a depletion layer is stopped in the middle of the N cathode buffer layer, and thus prevented from reaching the N+ cathode layer, so that the leakage current is suppressed.
摘要翻译：一种半导体器件的制造方法，其特征在于，通过研磨使基板变薄，进行离子注入。在其中在N漂移层右侧形成有P阳极层和阳极电极的二极管中，在N的背面侧形成N +阴极层和阴极电极 - 漂移层，与N型漂移层和N +阴极层之间的N +型阴极层相比，形成较厚的N阴极缓冲层，与N漂移层相比，缓冲层的浓度高; 低于N +阴极层。当施加反向偏置电压时，耗尽层在N阴极缓冲层的中间停止，从而防止到达N +阴极层，从而抑制漏电流。

6. 发明授权

US07572683B2 Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices 有权
标题翻译：半导体器件及其制造方法，以及使用半导体器件的双向开关器件
公开(公告)号：US07572683B2
公开(公告)日：2009-08-11
申请号：US11558065
申请日：2006-11-09
申请人： Manabu Takei , Tatsuya Naito , Michio Nemoto
发明人： Manabu Takei , Tatsuya Naito , Michio Nemoto
IPC分类号： H01L21/331
CPC分类号： H02M7/003 , H01L29/0696 , H01L29/7395 , H01L29/872
摘要： A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n−-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.
摘要翻译：公开了一种半导体器件，其减少由反向偏置电压施加引起的反向泄漏电流并且降低IGBT的导通电压。提供了使用半导体器件的双向开关器件，并且公开了半导体器件的制造方法。反向阻断IGBT通过将p型基极区域和发射极之间延伸的n型漂移区域1的部分引入肖特基接触来形成肖特基结，从而减小反向漏电流和导通电压。

7. 发明授权

US07358127B2 Power semiconductor rectifier having broad buffer structure and method of manufacturing thereof 有权
标题翻译：具有宽缓冲结构的功率半导体整流器及其制造方法
公开(公告)号：US07358127B2
公开(公告)日：2008-04-15
申请号：US11339900
申请日：2006-01-26
申请人： Michio Nemoto
发明人： Michio Nemoto
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7802 , H01L21/263 , H01L29/0878 , H01L29/167 , H01L29/32 , H01L29/36 , H01L29/7395 , H01L29/7416 , H01L29/744 , H01L29/7813 , H01L29/861 , H01L29/868 , H01L29/872
摘要： Impurity concentration (Nd(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of the anode electrode and the cathode electrode. A ratio of the peak impurity concentration Np to an averaged impurity concentration Ndm in the n-drift layer is in the range of 1 to 5. This provides a diode and a manufacturing method thereof by which oscillations in voltage and current at reverse recovery are inhibited to achieve enhancement both in high speed and low-loss characteristics and in soft recovery characteristics.
摘要翻译：在二极管的n漂移层中的杂质浓度（N sub（X））在从阳极到阳极的方向与阳极的距离Xp处的位置处最大并且从朝向每个阳极电极和阴极电极的位置逐渐减小。 n漂移层中的杂质浓度N P p P N与平均杂质浓度N dm的比值在1至5的范围内。这提供二极管和抑制反向恢复的电压和电流的振荡的制造方法能够实现高速度，低损耗特性和软恢复特性的提高。

8. 发明授权

US07307330B2 Reverse blocking semiconductor device and a method for manufacturing the same 有权
标题翻译：反向阻挡半导体器件及其制造方法
公开(公告)号：US07307330B2
公开(公告)日：2007-12-11
申请号：US11397478
申请日：2006-04-04
申请人： Michio Nemoto , Manabu Takei , Tatsuya Naito
发明人： Michio Nemoto , Manabu Takei , Tatsuya Naito
IPC分类号： H01L23/58
CPC分类号： H01L29/0646 , H01L29/0619 , H01L29/0638 , H01L29/0834 , H01L29/404 , H01L29/7395
摘要： A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n− drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure. A p+ isolation region surrounds the MOS gate structure through the drift layer and extends across whole thickness of the drift layer. A p+ collector layer is formed on a rear surface of the drift layer and connects to a rear side of the isolation region. A distance W is greater than a thickness d, in which the distance W is a distance from an outermost position of a portion of the emitter electrode, the portion being in contact with the base layer, to an innermost position of the isolation region, and the thickness d is a dimension in a depth direction of the drift layer.
摘要翻译：没有显示隔离区域对反向恢复峰值电流的不利影响的反向阻挡半导体器件，其具有显示令人满意的软恢复的击穿耐受结构，其抑制基本上伴随常规反向阻断IGBT的反向漏电流的恶化，并且公开了令人满意的低导通电压。该器件包括形成在n漂移层上的MOS栅极结构，该MOS栅极结构包括形成在该漂移层的前表面区域中的p +基极层，形成在该基极层的表面区域中的n +发射极区域，覆盖发射极区域和漂移层之间的基底层的表面区域的栅极绝缘膜，以及形成在栅极绝缘膜上的栅电极。发射极电极与MOS栅极结构的发射极区域和基极层接触。 p +隔离区域通过漂移层包围MOS栅极结构，并延伸穿过漂移层的整个厚度。 p +集电极层形成在漂移层的后表面上并连接到隔离区的后侧。距离W大于厚度d，其中距离W是距离发射电极的一部分的最外侧位置（与基层接触的部分）到隔离区域的最内位置的距离，以及厚度d是漂移层的深度方向的尺寸。

9. 发明申请

US20050082640A1 Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices 有权
标题翻译：半导体器件及其制造方法，以及使用半导体器件的双向开关器件
公开(公告)号：US20050082640A1
公开(公告)日：2005-04-21
申请号：US10928927
申请日：2004-08-27
申请人： Manabu Takei , Tatsuya Naito , Michio Nemoto
发明人： Manabu Takei , Tatsuya Naito , Michio Nemoto
IPC分类号： H01L29/06 , H01L29/739 , H01L29/872 , H02M7/00 , H01L29/417
CPC分类号： H02M7/003 , H01L29/0696 , H01L29/7395 , H01L29/872
摘要： A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n−-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.
摘要翻译：公开了一种半导体器件，其减少由反向偏置电压施加引起的反向泄漏电流并且降低IGBT的导通电压。提供了使用半导体器件的双向开关器件，并且公开了制造半导体器件的方法。反向阻断IGBT通过将p型基极区域和发射极电极之间延伸的类型漂移区域1的部分引入肖特基接触来形成反向漏电流和导通电压，形成肖特基路口。

10. 发明授权

US10068998B2 Semiconductor device and method of producing the same 有权
公开(公告)号：US10068998B2
公开(公告)日：2018-09-04
申请号：US13299870
申请日：2011-11-18
申请人： Michio Nemoto , Haruo Nakazawa
发明人： Michio Nemoto , Haruo Nakazawa
IPC分类号： H01L21/26 , H01L21/42 , H01L29/739 , H01L29/32 , H01L29/66 , H01L29/36 , H01L21/263 , H01L29/10
摘要： A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N+ first buffer layer and an N second buffer layer. Then, a P+ collector layer and a collector electrode are formed on the proton-irradiated surface. The distance from a position where the net doping concentration of the N+ first buffer layer is locally maximized to the interface between the P+ collector layer and the N second buffer layer is set to be in a range of 5 μm to 30 μm, both inclusively.

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