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1. 发明授权

US10789182B2 System and method for individual addressing 有权
公开(公告)号：US10789182B2
公开(公告)日：2020-09-29
申请号：US16726523
申请日：2019-12-24
申请人： Micron Technology, Inc.
发明人： Debra Bell , Paul Glendenning , David R. Brown , Harold B Noyes
IPC分类号： G06F15/00 , G06F13/12 , G06F13/28 , G06F13/40
摘要： In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

2. 发明授权

US10268602B2 System and method for individual addressing 有权
公开(公告)号：US10268602B2
公开(公告)日：2019-04-23
申请号：US15280611
申请日：2016-09-29
申请人： Micron Technology, Inc.
发明人： Debra Bell , Paul Glendenning , David R. Brown , Harold B Noyes
IPC分类号： G06F12/02 , G06F13/12 , G06F13/28 , G06F13/40
摘要： In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

3. 发明申请

US20180122439A1 METHODS AND APPARATUSES FOR COMMAND SHIFTER REDUCTION 审中-公开
公开(公告)号：US20180122439A1
公开(公告)日：2018-05-03
申请号：US15857597
申请日：2017-12-28
申请人： Micron Technology, Inc.
发明人： Debra Bell , Kallol Mazumder
IPC分类号： G11C7/22 , G06F9/30 , G11C7/10
CPC分类号： G11C7/22 , G06F9/30156 , G11C7/109 , G11C2207/2272
摘要： Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

4. 发明申请

US20160314823A1 METHODS AND APPARATUSES FOR COMMAND SHIFTER REDUCTION 有权
标题翻译：指令减少的方法和设备
公开(公告)号：US20160314823A1
公开(公告)日：2016-10-27
申请号：US14693769
申请日：2015-04-22
申请人： Micron Technology, Inc.
发明人： Debra Bell , Kallol Mazumder
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C7/22 , G06F9/30156 , G11C7/109 , G11C2207/2272
摘要： Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.
摘要翻译：公开了用于减少多个命令移位器的装置和方法。示例性设备包括编码器电路，等待时间移位器电路和解码器电路。编码器电路可以被配置为对命令进行编码，其中根据命令类型对命令进行编码，并且耦合到编码器电路的等待时间移位器电路可被配置为为已编码的命令提供等待时间。耦合到等待时间移位器电路的解码器电路可以被配置为对编码的命令进行解码，并提供解码的命令以执行与解码的命令的命令类型相关联的存储器操作。

5. 发明授权

US09294105B2 Delay line off-state control with power reduction 有权
公开(公告)号：US09294105B2
公开(公告)日：2016-03-22
申请号：US14083875
申请日：2013-11-19
申请人： Micron Technology, Inc.
发明人： Tyler J. Gomm , Debra Bell
IPC分类号： H03L7/08 , G11C7/22 , H03L7/081
CPC分类号： H03L7/0802 , G11C7/22 , G11C7/222 , H03L7/0814
摘要： A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

6. 发明授权

US10825492B2 Methods and apparatuses for command shifter reduction 有权
公开(公告)号：US10825492B2
公开(公告)日：2020-11-03
申请号：US16416425
申请日：2019-05-20
申请人： MICRON TECHNOLOGY, INC.
发明人： Debra Bell , Kallol Mazumder
IPC分类号： G11C7/10 , G11C7/22 , G06F9/30
摘要： Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

7. 发明授权

US10521366B2 System and method for individual addressing 有权
公开(公告)号：US10521366B2
公开(公告)日：2019-12-31
申请号：US16400739
申请日：2019-05-01
申请人： Micron Technology, Inc.
发明人： Debra Bell , Paul Glendenning , David R. Brown , Harold B Noyes
IPC分类号： G06F12/10 , G06F13/12 , G06F13/40 , G06F13/28
摘要： In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

8. 发明申请

US20190258592A1 SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING 审中-公开
公开(公告)号：US20190258592A1
公开(公告)日：2019-08-22
申请号：US16400739
申请日：2019-05-01
申请人： Micron Technology, Inc.
发明人： Debra Bell , Paul Glendenning , David R. Brown , Harold B Noyes
IPC分类号： G06F13/12 , G06F13/40 , G06F13/28
摘要： In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

9. 发明授权

US10339071B2 System and method for individual addressing 有权
公开(公告)号：US10339071B2
公开(公告)日：2019-07-02
申请号：US16192509
申请日：2018-12-10
申请人： Micron Technology, Inc.
发明人： Debra Bell , Paul Glendenning , David R. Brown , Harold B Noyes
IPC分类号： G06F12/00 , G06F13/12 , G06F13/28 , G06F13/40
摘要： In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

10. 发明申请

US20200133893A1 SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING 审中-公开
公开(公告)号：US20200133893A1
公开(公告)日：2020-04-30
申请号：US16726523
申请日：2019-12-24
申请人： Micron Technology, Inc.
发明人： Debra Bell , Paul Glendenning , David R. Brown , Harold B Noyes
IPC分类号： G06F13/12 , G06F13/40 , G06F13/28
摘要： In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

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