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1. 发明公开

US20230176869A1 METHOD OF IMPLEMENTING AN ARM64-BIT FLOATING POINT EMULATOR ON A LINUX SYSTEM 审中-公开
公开(公告)号：US20230176869A1
公开(公告)日：2023-06-08
申请号：US17736140
申请日：2022-05-04
申请人： Airoha Technology (Suzhou) Limited
发明人： Fei YAN , Peng DU
IPC分类号： G06F9/30
CPC分类号： G06F9/30076 , G06F9/30156 , G06F9/3013
摘要： The present invention provides a method of implementing an ARM64-bit floating point emulator on a Linux system, which includes: running an ARM64-bit instruction on the Linux system; applying an instruction classifier to a first feature code of a machine code indicated by the ARM64-bit instruction to determine whether the ARM64-bit instruction is an ARM64-bit floating point instruction; and, if the ARM64-bit instruction is an ARM64-bit floating point instruction, applying the instruction classifier to a second feature code of the machine code indicated by the ARM64-bit instruction to determine the ARM64-bit floating instruction to be a specific ARM64-bit floating instruction.

2. 发明申请

US20190250919A1 METHOD FOR MANAGING COMPUTATION TASKS ON A FUNCTIONALLY ASYMMETRIC MULTI-CORE PROCESSOR 审中-公开
公开(公告)号：US20190250919A1
公开(公告)日：2019-08-15
申请号：US16333974
申请日：2017-09-06
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Karim BEN CHEHIDA , Paul-Antoine ARRAS
IPC分类号： G06F9/30 , G06F9/50 , G06F9/48 , G06F1/3228 , G06F9/38
CPC分类号： G06F9/30156 , G06F1/3228 , G06F9/3885 , G06F9/4881 , G06F9/5038 , G06F9/5044 , G06F2209/509 , Y02D10/24
摘要： A method for managing a computation task on a functionally asymmetric multi-core processor includes a plurality of cores at least one of which comprises at least one hardware extension for executing specialized instructions, comprising the following steps: a) starting the execution of the computation task on a core of the processor; b) monitoring a parameter indicative of a quality of service of the computation task, and at least a number of specialized instructions loaded by the core; c) identifying instants splitting an application period of the computation task into a predetermined number of portions; d) computing costs or gains in quality of service and in energy consumption corresponding to different management options of the computation task; and e) making a management choice according to the costs or gains thus computed. Computer program product, processor and computer system for implementing such a method are also provided.

3. 发明申请

US20170235576A1 METHOD AND APPARATUS FOR SPECULATIVE DECOMPRESSION 审中-公开
公开(公告)号：US20170235576A1
公开(公告)日：2017-08-17
申请号：US15371091
申请日：2016-12-06
申请人： Intel Corporation
发明人： SUDHIR K. SATPATHY , SANU K. MATHEW , VINODH GOPAL , JAMES D. GUILFORD
IPC分类号： G06F9/30 , H03M7/30 , H03M7/40
CPC分类号： G06F9/30185 , G06F9/30021 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30156 , G06F9/3016 , H03M7/4037 , H03M7/6005 , H03M7/6023
摘要： An apparatus and method for performing parallel decoding of prefix codes such as Huffman codes. For example, one embodiment of an apparatus comprises: a first decompression module to perform a non-speculative decompression of a first portion of a prefix code payload comprising a first plurality of symbols; and a second decompression module to perform speculative decompression of a second portion of the prefix code payload comprising a second plurality of symbols concurrently with the non-speculative decompression performed by the first compression module.

4. 发明授权

US09672042B2 Processing system and method of instruction set encoding space utilization 有权
公开(公告)号：US09672042B2
公开(公告)日：2017-06-06
申请号：US14396146
申请日：2012-05-29
申请人： Roy Glasner , Itzhak Barak , Yuval Peled , Idan Rozenberg , Lev Vaskevich
发明人： Roy Glasner , Itzhak Barak , Yuval Peled , Idan Rozenberg , Lev Vaskevich
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30196 , G06F9/30145 , G06F9/30156 , G06F9/3853
摘要： A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions.

5. 发明申请

US20170147343A1 METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM 审中-公开
公开(公告)号：US20170147343A1
公开(公告)日：2017-05-25
申请号：US15396578
申请日：2016-12-31
申请人： Intel Corporation
发明人： Kirk S. YAP , Gilbert M. WOLRICH , James D. GUILFORD , Vinodh GOPAL , Erdinc OZTURK , Sean M. GULLEY , Wajdi K. FEGHALI , Martin G. DIXON
IPC分类号： G06F9/30 , G06F9/38 , G06F12/0897 , H04L9/06 , G06F12/1027 , G06F13/40 , G06F13/42 , G06F15/80 , G06F12/0875
CPC分类号： G06F21/602 , G06F9/30007 , G06F9/30036 , G06F9/30098 , G06F9/30156 , G06F9/3016 , G06F9/384 , G06F9/3855 , G06F12/0875 , G06F12/0897 , G06F12/1027 , G06F13/28 , G06F13/4068 , G06F13/4282 , G06F15/8007 , G06F2212/452 , G06F2212/68 , G06F2213/0026 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/122
摘要： A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

6. 发明申请

US20160321076A1 METHOD AND APPARATUS FOR SPECULATIVE DECOMPRESSION 有权
标题翻译：用于测量分解的方法和装置
公开(公告)号：US20160321076A1
公开(公告)日：2016-11-03
申请号：US14698486
申请日：2015-04-28
申请人： Intel Corporation
发明人： SUDHIR K. SATPATHY , SANU K. MATHEW , VINODH GOPAL , JAMES D. GUILFORD
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/30021 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/30156 , G06F9/3016 , H03M7/4037 , H03M7/6005 , H03M7/6023
摘要： An apparatus and method for performing parallel decoding of prefix codes such as Huffman codes. For example, one embodiment of an apparatus comprises: a first decompression module to perform a non-speculative decompression of a first portion of a prefix code payload comprising a first plurality of symbols; and a second decompression module to perform speculative decompression of a second portion of the prefix code payload comprising a second plurality of symbols concurrently with the non-speculative decompression performed by the first compression module.
摘要翻译：一种用于执行诸如霍夫曼码之类的前缀码的并行解码的装置和方法。例如，装置的一个实施例包括：第一解压缩模块，用于执行包括第一多个符号的前缀码有效载荷的第一部分的非推测解压缩; 以及第二解压缩模块，用于执行与由第一压缩模块执行的非推测性解压缩同时地包括第二多个符号的前缀码有效载荷的第二部分的推测性解压缩。

7. 发明授权

US09348593B2 Instruction address encoding and decoding based on program construct groups 有权
标题翻译：基于程序构造组的指令地址编码和解码
公开(公告)号：US09348593B2
公开(公告)日：2016-05-24
申请号：US13596381
申请日：2012-08-28
申请人： Prakash Krishnamoorthy , Ramesh C. Tekumalla , Parag Madhani
发明人： Prakash Krishnamoorthy , Ramesh C. Tekumalla , Parag Madhani
IPC分类号： G06F9/30 , G06F9/32 , G06F9/34 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/30156 , G06F9/32 , G06F9/322 , G06F9/34 , G06F9/3806
摘要： Coding circuitry comprises at least an encoder configured to encode an instruction address for transmission to a decoder. The encoder is operative to identify the instruction address as belonging to a particular one of a plurality of groups of instruction addresses associated with respective distinct program constructs, and to encode the instruction address based on the identified group. The decoder is operative to identify the encoded instruction address as belonging to the particular one of a plurality of groups of instruction addresses associated with respective distinct program constructs, and to decode the encoded instruction address based on the identified group. The coding circuitry may be implemented as part of an integrated circuit or other processing device that includes associated processor and memory elements. In such an arrangement, the processor may generate the instruction address for delivery over a bus to the memory.
摘要翻译：编码电路至少包括编码器，该编码器被配置为编码用于传输到解码器的指令地址。编码器用于将指令地址识别为属于与各个不同节目构造相关联的多组指令地址中的特定一个，并且基于所识别的组对指令地址进行编码。解码器用于将编码的指令地址识别为属于与各个不同节目构造相关联的多组指令地址中的特定一个，并且基于所识别的组对编码的指令地址进行解码。编码电路可以被实现为集成电路或包括相关联的处理器和存储器元件的其他处理设备的一部分。在这种布置中，处理器可以产生用于通过总线传送到存储器的指令地址。

8. 发明授权

US09268573B2 Methods for decoding and dispatching program instructions 有权
标题翻译：解码和调度程序指令的方法
公开(公告)号：US09268573B2
公开(公告)日：2016-02-23
申请号：US13667192
申请日：2012-11-02
申请人： Michael Rolle , Stanley Goldberg
发明人： Michael Rolle , Stanley Goldberg
IPC分类号： G06F15/177 , G06F9/30
CPC分类号： G06F9/30156 , G06F9/30149
摘要： Methods for encoding a program. Each program instruction in a program has one or more possible encodings, and each instruction encoding may have a different length. The instruction encodings are selected such that the resulting encoding of the program as a whole minimizes the number of program cycles used in a decoding stage of a processor. Instruction padding or program padding may be used to create instruction encodings of lengths.
摘要翻译：编码程序的方法。程序中的每个程序指令具有一个或多个可能的编码，并且每个指令编码可以具有不同的长度。指令编码被选择为使得程序的结果编码整体最小化处理器的解码级中使用的程序周期的数量。指令填充或程序填充可用于创建长度的指令编码。

9. 发明授权

US09223576B2 Reducing a set of instructions for execution on a processor and expanding a set of instructions on a processor 有权
标题翻译：减少用于在处理器上执行的指令集，并在处理器上扩展一组指令
公开(公告)号：US09223576B2
公开(公告)日：2015-12-29
申请号：US13340379
申请日：2011-12-29
申请人： Peter Smith , David Richard Hargreaves
发明人： Peter Smith , David Richard Hargreaves
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30156 , G06F9/30178 , G06F9/30185
摘要： A method of reducing a set of instructions for execution on a processor extracts information from a first instruction of the set of instructions. The method identifies unencoded space in one or more further instructions of the set of instructions and replaces the unencoded space of the one or more further instructions with the extracted information of the first instruction so as to form one or more amalgamated instructions. The method removes the first instruction from the set of instructions. A method of expanding a set of reduced instructions on a processor is also disclosed.
摘要翻译：一种减少用于在处理器上执行的指令集的方法从该组指令的第一指令中提取信息。该方法识别该组指令中的一个或多个其它指令中的未编码空间，并用所提取的第一指令的信息替换一个或多个其他指令的未编码空间，以便形成一个或多个合并指令。该方法从指令集中删除第一条指令。还公开了一种在处理器上扩展一组简化指令的方法。

10. 发明授权

US08954941B2 Method and apparatus and record carrier 有权
标题翻译：方法和装置和记录载体
公开(公告)号：US08954941B2
公开(公告)日：2015-02-10
申请号：US13393823
申请日：2010-09-03
申请人： Hendrik Tjeerd Joannes Zwartenkot , Alexander Augusteijn , Yuanging Guo , Jürgen Von Oerthel , Jeroen Anton Johan Leijten , Erwan Yann Maurice Le Thenaff
发明人： Hendrik Tjeerd Joannes Zwartenkot , Alexander Augusteijn , Yuanging Guo , Jürgen Von Oerthel , Jeroen Anton Johan Leijten , Erwan Yann Maurice Le Thenaff
IPC分类号： G06F9/45 , G06F15/76 , G06F9/30
CPC分类号： G06F9/3017 , G06F8/4434 , G06F9/30156 , G06F9/30167 , G06F9/30178
摘要： Method of generating respective instruction compaction schemes for subsets of instructions to be processed by a programmable processor, comprising the steps of a) receiving at least one input code sample representative for software to be executed on the programmable processor, the input code comprising a plurality of instructions defining a first set of instructions (S1), b) initializing a set of removed instructions as empty (S3), c) determining the most compact representation of the first set of instructions (S4) d) comparing the size of said most compact representation with a threshold value (S5), e) carrying out steps e1 to e3 if the size is larger than said threshold value, e1) determining which instruction of the first set of instructions has a highest coding cost (S6), e2) removing said instruction having the highest coding cost from the first set of instructions and (S7), e3) adding said instruction to the set of removed instructions (S8), f) repeating steps b-f, wherein the first set of instructions is formed by the set of removed instructions (S9, S10).
摘要翻译：为由可编程处理器处理的指令的子集产生相应的指令压缩方案的方法，包括以下步骤：a）接收代表要在可编程处理器上执行的软件的至少一个输入代码样本，所述输入代码包括多个定义第一组指令（S1）的指令，b）将一组去除的指令初始化为空（S3），c）确定第一组指令的最紧凑的表示（S4）d）将所述最紧凑的指令的大小进行比较具有阈值（S5）的表示，e）如果尺寸大于所述阈值，执行步骤e1至e3，e1）确定第一组指令的哪个指令具有最高编码成本（S6），e2）去除所述指令具有来自第一组指令的编码成本最高（S7），e3）将所述指令加到删除的指令集上（S8），f）重复步骤bf，其中fi 第一组指令由删除的指令集（S9，S10）形成。

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