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1. 发明授权

US11625197B2 Memory sub-system for increasing bandwidth for command scheduling 有权
公开(公告)号：US11625197B2
公开(公告)日：2023-04-11
申请号：US17498415
申请日：2021-10-11
申请人： Micron Technology, Inc.
发明人： Patrick A. La Fratta , Robert Walker
IPC分类号： G06F3/06
摘要： Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

2. 发明授权

US11567700B2 Memory sub-system for supporting deterministic and non-deterministic commands based on command expiration and the state of the intermediate command queue 有权
公开(公告)号：US11567700B2
公开(公告)日：2023-01-31
申请号：US17223684
申请日：2021-04-06
申请人： Micron Technology, Inc.
发明人： Patrick A. La Fratta , Robert Walker
IPC分类号： G06F3/06
摘要： Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

3. 发明授权

US11016885B2 Memory sub-system for decoding non-power-of-two addressable unit address boundaries 有权
公开(公告)号：US11016885B2
公开(公告)日：2021-05-25
申请号：US16285909
申请日：2019-02-26
申请人： Micron Technology, Inc.
发明人： Patrick A. La Fratta , Robert Walker , Chandrasekhar Nagarajan
IPC分类号： G06F13/00 , G06F13/28 , G06F12/06 , G06F12/04 , G06F9/30
摘要： A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

4. 发明授权

US10990321B2 Memory sub-system for supporting deterministic and non-deterministic commands based on command expiration and the state of the intermediate command queue 有权
公开(公告)号：US10990321B2
公开(公告)日：2021-04-27
申请号：US16280607
申请日：2019-02-20
申请人： Micron Technology, Inc.
发明人： Patrick A. La Fratta , Robert Walker
IPC分类号： G06F3/06
摘要： Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

5. 发明申请

US20200293438A1 SYSTEMS AND METHODS FOR MEMORY SYSTEM MANAGEMENT 审中-公开
公开(公告)号：US20200293438A1
公开(公告)日：2020-09-17
申请号：US16886252
申请日：2020-05-28
申请人： Micron Technology, Inc.
发明人： Robert Walker , David A. Roberts
IPC分类号： G06F12/02 , G06F3/06 , G11C7/04 , G06F1/20 , G06F1/3234 , G06F12/122 , G06F13/24 , G06F13/16 , G06F13/42
摘要： Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

6. 发明授权

US10042750B2 Apparatuses and methods for adaptive control of memory using an adaptive memory controller with a memory management hypervisor 有权
公开(公告)号：US10042750B2
公开(公告)日：2018-08-07
申请号：US13911797
申请日：2013-06-06
申请人： Micron Technology, Inc.
发明人： David A. Roberts , J. Thomas Pawlowski , Robert Walker
IPC分类号： G06F12/00 , G06F12/02 , G06F13/16
摘要： Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.

7. 发明申请

US20160041785A1 CONTROL OF PAGE ACCESS IN MEMORY 有权
公开(公告)号：US20160041785A1
公开(公告)日：2016-02-11
申请号：US14918364
申请日：2015-10-20
申请人： Micron Technology, Inc.
发明人： Robert Walker
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0604 , G06F3/061 , G06F3/0644 , G06F3/0688 , G06F3/0689 , G06F12/00 , G06F12/0215 , G06F12/06 , G06F12/14 , G06F13/00 , G06F13/14 , G06F13/16 , G06F13/161 , G06F13/1615 , G06F13/1668 , G06F13/4243 , G06F15/7821 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.

8. 发明申请

US20140281311A1 SYSTEMS AND METHODS FOR MEMORY SYSTEM MANAGEMENT BASED ON THERMAL INFORMATION OF A MEMORY SYSTEM 有权
标题翻译：基于存储器系统的热信息的存储器系统管理的系统和方法
公开(公告)号：US20140281311A1
公开(公告)日：2014-09-18
申请号：US14055672
申请日：2013-10-16
申请人： Micron Technology, Inc.
发明人： Robert Walker , David A. Roberts
IPC分类号： G06F3/06
CPC分类号： G06F12/0223 , G06F1/206 , G06F1/3275 , G06F3/0604 , G06F3/0631 , G06F3/0673 , G06F12/023 , G06F12/122 , G06F13/1668 , G06F13/24 , G06F13/4282 , G06F2212/1016 , G11C7/04 , G11C11/40626 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/16
摘要： Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.
摘要翻译：描述了将存储区域映射到基于存储器区域的热数据的处理的方法。在一些实施例中，存储器控制器可以接收存储器分配请求。存储器分配请求可以包括逻辑存储器地址。该方法还可以包括基于存储器系统的存储器区域的热数据将逻辑存储器地址映射到存储器系统的存储器区域中的地址。还描述了附加的方法和系统。

9. 发明申请

US20140281149A1 APPARATUSES AND METHODS FOR ADAPTIVE CONTROL OF MEMORY 审中-公开
标题翻译：记忆自适应控制的装置和方法
公开(公告)号：US20140281149A1
公开(公告)日：2014-09-18
申请号：US13911797
申请日：2013-06-06
申请人： Micron Technology, Inc.
发明人： David A. Roberts , J. Thomas Pawlowski , Robert Walker
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/023 , G06F12/0292 , G06F13/1694 , Y02D10/13 , Y02D10/14
摘要： Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.
摘要翻译：公开了用于存储器自适应控制的装置和方法。一个示例性装置包括被配置为运行操作系统的处理单元和耦合到处理单元的存储器。所述存储器经配置以经由存储器总线与所述处理单元通信。示例设备还可以包括自适应存储器控制器，其被配置为从存储器和处理单元接收监视的统计数据。自适应存储器控制器被配置为基于所监视的统计数据来管理存储器。

10. 发明申请

US20130318294A1 INTERNAL PROCESSOR BUFFER 有权
标题翻译：内部处理器缓冲器
公开(公告)号：US20130318294A1
公开(公告)日：2013-11-28
申请号：US13960634
申请日：2013-08-06
申请人： Micron Technology, Inc.
发明人： Robert Walker
IPC分类号： G11C19/00
CPC分类号： G11C19/00 , G06F9/3877 , G06F15/7821 , G06F15/785 , Y02D10/12 , Y02D10/13
摘要： One or more of the present techniques provide a compute engine buffer configured to maneuver data and increase the efficiency of a compute engine. One such compute engine buffer is connected to a compute engine which performs operations on operands retrieved from the buffer, and stores results of the operations to the buffer. Such a compute engine buffer includes a compute buffer having storage units which may be electrically connected or isolated, based on the size of the operands to be stored and the configuration of the compute engine. The compute engine buffer further includes a data buffer, which may be a simple buffer. Operands may be copied to the data buffer before being copied to the compute buffer, which may save additional clock cycles for the compute engine, further increasing the compute engine efficiency.
摘要翻译：一种或多种本技术提供了一种配置成操纵数据并提高计算引擎效率的计算引擎缓冲器。一个这样的计算引擎缓冲器连接到计算引擎，该计算引擎对从缓冲器检索的操作数执行操作，并将操作的结果存储到缓冲器。这样的计算引擎缓冲器包括基于要存储的操作数的大小和计算引擎的配置的具有可以电连接或隔离的存储单元的计算缓冲器。计算引擎缓冲器还包括数据缓冲器，其可以是简单的缓冲器。在复制到计算缓冲区之前，操作数可以复制到数据缓冲区，这可能为计算引擎节省额外的时钟周期，进一步提高了计算引擎的效率。

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