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1. 发明授权

US11587948B2 Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies 有权
公开(公告)号：US11587948B2
公开(公告)日：2023-02-21
申请号：US17369605
申请日：2021-07-07
申请人： Micron Technology, Inc.
发明人： Shyam Surthi , Richard J. Hill , Byeung Chul Kim , Akira Goda
IPC分类号： H01L27/11556 , H01L27/11582 , H01L29/51 , H01L29/792 , H01L21/28 , H01L29/49 , H01L29/788
摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

2. 发明授权

US11557608B2 Integrated assemblies having vertically-spaced channel material segments, and methods of forming integrated assemblies 有权
公开(公告)号：US11557608B2
公开(公告)日：2023-01-17
申请号：US17393664
申请日：2021-08-04
申请人： Micron Technology, Inc.
发明人： Byeung Chul Kim , Francois H. Fabreguette , Richard J. Hill , Shyam Surthi
IPC分类号： H01L27/11582 , H01L27/11556 , H01L29/51 , H01L29/49 , H01L21/28 , H01L29/792 , H01L21/02 , H01L29/788
摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

3. 发明授权

US11296103B2 Integrated assemblies and methods of forming integrated assemblies 有权
公开(公告)号：US11296103B2
公开(公告)日：2022-04-05
申请号：US16863000
申请日：2020-04-30
申请人： Micron Technology, Inc.
发明人： Shyam Surthi , Kunal Shrotri , Matthew Thorum
IPC分类号： H01L27/11578 , H01L27/1157 , H01L27/11524 , H01L27/11582 , H01L27/11556 , H01L27/11565 , H01L27/11519
摘要： Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

4. 发明申请

US20210233933A1 Integrated Assemblies Having Vertically-Spaced Channel Material Segments, and Methods of Forming Integrated Assemblies 有权
公开(公告)号：US20210233933A1
公开(公告)日：2021-07-29
申请号：US17230541
申请日：2021-04-14
申请人： Micron Technology, Inc.
发明人： John D. Hopkins , Shyam Surthi , Jordan D. Greenlee
IPC分类号： H01L27/11582 , H01L29/49 , H01L29/51 , H01L21/28 , H01L29/792 , H01L29/788 , H01L21/02 , H01L27/11556
摘要： Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

5. 发明申请

US20200373325A1 Integrated Assemblies Having Charge-Trapping Material Arranged in Vertically-Spaced Segments, and Methods of Forming Integrated Assemblies 审中-公开
公开(公告)号：US20200373325A1
公开(公告)日：2020-11-26
申请号：US16988548
申请日：2020-08-07
申请人： Micron Technology, Inc.
发明人： Byeung Chul Kim , Francois H. Fabreguette , Richard J. Hill , Purnima Narayanan , Shyam Surthi
IPC分类号： H01L27/11582 , H01L27/1157 , G11C16/08 , H01L21/02
摘要： Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

6. 发明授权

US09559201B2 Vertical memory devices, memory arrays, and memory devices 有权
标题翻译：垂直存储器件，存储器阵列和存储器件
公开(公告)号：US09559201B2
公开(公告)日：2017-01-31
申请号：US14718785
申请日：2015-05-21
申请人： Micron Technology, Inc.
发明人： Shyam Surthi
IPC分类号： H01L27/108 , H01L29/78 , H01L29/66 , H01L21/762 , H01L21/764 , H01L29/423
CPC分类号： H01L29/7827 , H01L21/76232 , H01L21/764 , H01L27/10876 , H01L27/10891 , H01L29/4236 , H01L29/66666
摘要： Vertical memory devices comprise vertical transistors in an array region and digit lines extending in a first direction and comprising a source region or a drain region of at least some of the vertical transistors. The vertical memory devices further include word lines extending in a second direction along sidewalls of the vertical transistors and along sidewalls of columns of an oxide material in a word line end region. The wordlines extend closer to an upper surface of the vertical memory device on the sidewalls of the oxide material than on the sidewalls of the vertical transistors. Memory arrays comprising vertical transistors in an array region, digit line, and word lines are disclosed, as are memory devices comprising transistors in an array region, digit lines, and word lines.
摘要翻译：垂直存储器件包括阵列区域中的垂直晶体管和沿第一方向延伸并且包括至少一些垂直晶体管的源极区域或漏极区域的数字线。垂直存储器件还包括沿垂直晶体管的侧壁沿着第二方向延伸的字线，并且沿着字线端部区域中的氧化物材料的列的侧壁延伸。字线在氧化物材料的侧壁上比垂直晶体管的侧壁更靠近垂直存储器件的上表面。公开了包括阵列区域，数字线和字线中的垂直晶体管的存储器阵列，以及包括阵列区域，数字线和字线中的晶体管的存储器件。

7. 发明授权

US09318493B2 Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions 有权
标题翻译：存储阵列，半导体结构以及形成半导体结构的方法
公开(公告)号：US09318493B2
公开(公告)日：2016-04-19
申请号：US14502978
申请日：2014-09-30
申请人： Micron Technology, Inc.
发明人： Lars P. Heineck , Shyam Surthi , Jaydip Guha
IPC分类号： H01L27/108 , H01L29/66 , H01L29/778 , H01L21/28 , H01L29/78
CPC分类号： H01L27/10802 , H01L21/28132 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/66666 , H01L29/7788 , H01L29/7827 , H01L29/7841
摘要： Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.
摘要翻译：一些实施例包括存储器阵列。存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。一些实施例包括形成存储器阵列的方法。可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

8. 发明申请

US20150206886A1 Methods of Forming Memory Arrays and Semiconductor Constructions 有权
标题翻译：形成记忆阵列和半导体结构的方法
公开(公告)号：US20150206886A1
公开(公告)日：2015-07-23
申请号：US14569337
申请日：2014-12-12
申请人： Micron Technology, Inc.
发明人： Jaydip Guha , Shyam Surthi
IPC分类号： H01L27/108 , H01L29/04 , H01L21/324 , H01L21/02 , H01L21/265 , H01L29/66 , H01L29/16
CPC分类号： H01L27/10876 , H01L21/02532 , H01L21/0257 , H01L21/02598 , H01L21/26513 , H01L21/324 , H01L21/8222 , H01L21/8229 , H01L21/823487 , H01L27/0814 , H01L27/0823 , H01L27/1021 , H01L27/1022 , H01L27/1052 , H01L27/1085 , H01L27/10894 , H01L27/10897 , H01L29/04 , H01L29/16 , H01L29/6609 , H01L29/66272 , H01L29/66666 , H01L29/732 , H01L29/868
摘要： Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
摘要翻译：一些实施例包括形成半导体结构的方法。在第一半导体材料内形成重掺杂区，并且在第一半导体材料上外延生长第二半导体材料。将第二半导体材料图案化以形成电路部件，并且对重掺杂区域进行图案化以形成将多个电路部件彼此电耦合的间隔开的掩埋线。至少一些重掺杂区域的图案化与第二半导体材料的至少一些图案化同时发生。

9. 发明申请

US20140017865A1 Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions 有权
标题翻译：存储阵列，半导体结构和形成半导体结构的方法
公开(公告)号：US20140017865A1
公开(公告)日：2014-01-16
申请号：US14030880
申请日：2013-09-18
申请人： Micron Technology, Inc.
发明人： Lars P Heineck , Shyam Surthi , Jaydip Guha
IPC分类号： H01L29/66
CPC分类号： H01L27/10802 , H01L21/28132 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/66666 , H01L29/7788 , H01L29/7827 , H01L29/7841
摘要： Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.
摘要翻译：一些实施例包括存储器阵列。存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。一些实施例包括形成存储器阵列的方法。可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。

10. 发明申请

US20130237023A1 Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith 有权
标题翻译：形成垂直晶体管的方法和至少一个导电线电耦合的方法
公开(公告)号：US20130237023A1
公开(公告)日：2013-09-12
申请号：US13869112
申请日：2013-04-24
申请人： MICRON TECHNOLOGY, INC.
发明人： Jaydip Guha , Shyam Surthi , Suraj J. Mathew , Kamal M. Karda , Hung-Ming Tsai
IPC分类号： H01L21/8234
CPC分类号： H01L21/823487 , H01L27/108 , H01L27/10876 , H01L27/1104 , H01L29/41741 , H01L29/66666 , H01L29/66825 , H01L29/66833
摘要： Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.
摘要翻译：沟槽形成半导体材料。遮蔽材料横向形成在沟槽的至少垂直内侧壁部分上。电导率改性杂质通过沟槽的基底注入到下面的半导体材料中。这种杂质被扩散到横向覆盖在沟槽的顶部内侧壁部分上的掩蔽材料中，并且被扩散到半导体材料中，该半导体材料被容纳在中间通道部分下方的沟槽之间。在中间通道部分下方的半导体材料中形成一个正面内部源极/漏极。内部源极/漏极部分包括在其中具有杂质的沟槽之间的所述半导体材料。导电线横向形成并电耦合到内源/漏的相对侧中的至少一个。栅极形成在导电线的正上方并与导电线隔开并且横向邻近中间通道部分。公开了其他实施例。

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