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1. 发明授权

US10069503B2 Method of speeding up output alignment in a digital phase locked loop 有权
公开(公告)号：US10069503B2
公开(公告)日：2018-09-04
申请号：US15597726
申请日：2017-05-17
申请人： Microsemi Semiconductor ULC
发明人： Changhui Cathy Zhang , Qu Gary Jin , Mark A. Warriner , Kamran Rahbar
IPC分类号： H03L7/06 , H03L7/10 , H03L7/18 , H03K5/135 , H03L7/099 , H03L7/091 , H03K5/00
摘要： To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

2. 发明申请

US20160294401A1 Hardware Delay Compensation in Digital Phase Locked Loop 有权
标题翻译：数字锁相环硬件延迟补偿
公开(公告)号：US20160294401A1
公开(公告)日：2016-10-06
申请号：US15064663
申请日：2016-03-09
申请人： Microsemi Semiconductor ULC
发明人： Qu Gary Jin , Paul H.L.M. Schram , Krste Mitric , Cathy Zhang , Gabriel Rusaneanu , Wenbao Wang
IPC分类号： H03L7/099 , H03L7/07 , H03K5/135 , H03L7/093
CPC分类号： H03K5/135 , H03K2005/00104 , H03L7/07 , H03L7/0805 , H03L7/081 , H03L7/085 , H03L7/093 , H03L2207/50
摘要： In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.
摘要翻译：在包括响应于控制值的第一软件实现的受控振荡器（SDCO）的PLL环路的数字锁相环中，以产生锁定到参考输入信号的输出相位和频率值，以及响应于输出的硬件实现的受控振荡器来自所述第一SDCO的相位和频率值以合成所述时钟信号，通过对所述合成时钟信号或其派生进行采样来补偿硬件延迟，以产生合成时钟相位值。将合成的时钟信号相位值与从PLL环路导出的反馈相位值进行比较，以产生修正合成时钟信号或其导数的补偿值。

3. 发明授权

US10128826B2 Clock synthesizer with integral non-linear interpolation (INL) distortion compensation 有权
公开(公告)号：US10128826B2
公开(公告)日：2018-11-13
申请号：US15824139
申请日：2017-11-28
申请人： Microsemi Semiconductor ULC
发明人： Qu Gary Jin , Kamran Rahbar
IPC分类号： H03B21/00 , H03K5/1252 , H03L7/099 , H03L7/091 , H03K5/00
摘要： A method of compensating for integral nonlinear interpolation (INL) distortion in a clock synthesizer driven by a system clock running at a frequency fsys, involves introducing a selected nominal analog delay I*dt with an actual delay of I*dt+δ at the output of the a first path with a digital controlled oscillator (DCO) and a digital-to-time converter (DTC) and a nominal digital delay I*D with an actual delay of I*D+Δ at the input of a second path with a DCO and a DTC that offsets the actual analog delay in the first path, adjusting the contents x(k) of a compensation module in the second path to align the output pulses of the first and second paths for different values of k, where k represents an interpolation point, iteratively repeating the two preceding steps for all N values of I, and averaging the contents x(k) of the compensation module to derive the compensation values to be applied to a one of the DTCs to correct for INL distortion.

4. 发明授权

US08941424B2 Digital phase locked loop with reduced convergence time 有权
标题翻译：数字锁相环减少了收敛时间
公开(公告)号：US08941424B2
公开(公告)日：2015-01-27
申请号：US14311638
申请日：2014-06-23
申请人： Microsemi Semiconductor ULC
发明人： Qu Gary Jin
IPC分类号： H03L7/06 , H03L7/093 , H03L7/14
CPC分类号： H03L7/093 , H03L7/1075 , H03L2207/50
摘要： A digital phase locked loop has a digital controlled oscillator, a phase comparator comparing the output signal of the digital controlled oscillator, or a signal derived therefrom, with a reference signal to produce a phase error signal. A loop filter produces a control signal for the digital controlled oscillator from an output of the phase comparator the loop filter. The loop filter has a proportional part producing a proportional component of the control signal, an integral part producing an integral component of the control signal, and an adder receiving the respective proportional and integral components at first and second inputs thereof to produce the control signal. The integral part includes a delayed feedback loop normally configured to accept the integral component at an input thereof. A first switch replaces the integral component at the input of the delayed feedback loop by the control signal in response to an activation signal. A control module produces the activation signal to activate the switch for brief periods when the phase error is non-zero and the rate of change of phase is less than a threshold value.
摘要翻译：数字锁相环具有数字控制振荡器，比较数字控制振荡器的输出信号或从其得到的信号的相位比较器与参考信号，以产生相位误差信号。环路滤波器从相位比较器的环路滤波器的输出产生数字控制振荡器的控制信号。环路滤波器具有比例部分，其产生控制信号的比例分量，产生控制信号的积分分量的积分部分和在其第一和第二输入处接收相应比例和积分分量的加法器，以产生控制信号。积分部分包括通常配置为在其输入处接受积分分量的延迟反馈回路。响应于激活信号，第一开关通过控制信号替代延迟反馈回路的输入处的积分分量。当相位误差不为零并且相位变化率小于阈值时，控制模块产生激活信号以激活开关短暂的时间段。

5. 发明申请

US20130191429A1 INFINITE IMPULSE RESPONSE FILTER ARCHITECTURE WITH IDLE-TONE REDUCTION 有权
标题翻译：无限风险反应滤波器结构，具有空调减少
公开(公告)号：US20130191429A1
公开(公告)日：2013-07-25
申请号：US13746573
申请日：2013-01-22
申请人： MICROSEMI SEMICONDUCTOR ULC
发明人： Qu Gary Jin
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , H03H17/0219 , H03H17/04
摘要： A digital infinite impulse response filter has a plurality of cascaded filter elements, with each filter element defining a pole of the filter and wherein the poles lie inside a unit circle. The filter elements are configured such that the p of the last filter element is a real number. In one embodiment the poles are arranged as complex conjugate pairs. In another embodiment the real part of the output of each filter element is extracted before being passed to the next filter element. This architecture offers improved idle tone with reduced complexity.
摘要翻译：数字无限脉冲响应滤波器具有多个级联的滤波器元件，每个滤波器元件限定滤波器的极点，并且其中极点位于单位圆内。滤波器元件被配置为使得最后一个滤波器元件的p是实数。在一个实施例中，极被布置为复共轭对。在另一个实施例中，每个滤波器元件的输出的实部在被传递到下一个滤波器元件之前被提取。该架构提供了改进的空闲音调，降低了复杂性

6. 发明授权

US09667237B2 Hardware delay compensation in digital phase locked loop 有权
公开(公告)号：US09667237B2
公开(公告)日：2017-05-30
申请号：US15064663
申请日：2016-03-09
申请人： Microsemi Semiconductor ULC
发明人： Qu Gary Jin , Paul H. L. M. Schram , Krste Mitric , Cathy Zhang , Gabriel Rusaneanu , Wenbao Wang
IPC分类号： H03L7/06 , H03K5/135 , H03L7/093 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/085 , H03K5/00
CPC分类号： H03K5/135 , H03K2005/00104 , H03L7/07 , H03L7/0805 , H03L7/081 , H03L7/085 , H03L7/093 , H03L2207/50
摘要： In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.

7. 发明授权

US09584138B2 Phase locked loop with accurate alignment among output clocks 有权
标题翻译：输出时钟之间具有精确对准的锁相环
公开(公告)号：US09584138B2
公开(公告)日：2017-02-28
申请号：US15091269
申请日：2016-04-05
申请人： Microsemi Semiconductor ULC
发明人： Krste Mitric , Qu Gary Jin , Guohui Situ , Paul H. L. M. Schram , Changhui Cathy Zhang , Richard Geiss
IPC分类号： H03L7/06 , H03L7/07 , H03L7/23 , H03L7/099 , H03L7/093 , H04L5/06
CPC分类号： H03L7/07 , H03L7/093 , H03L7/0991 , H03L7/23 , H04L5/06
摘要： A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.
摘要翻译：多通道锁相环（PLL）装置具有多个PLL通道。每个通道包括数字控制振荡器（DCO），通过输出分频器将输出时钟提供给相应的输出引脚。第一个复用器选择任何PLL通道进行对准。反馈校准PLL响应于在相应的输出引脚从所选通道的输出时钟导出的反馈信号。延迟控制模块响应反馈校准PLL的输出来调整输出时钟的相位。

8. 发明申请

US20160301417A1 Phase Locked Loop with Accurate Alignment among Output Clocks 有权
标题翻译：输出时钟之间精确对准的锁相环
公开(公告)号：US20160301417A1
公开(公告)日：2016-10-13
申请号：US15091269
申请日：2016-04-05
申请人： Microsemi Semiconductor ULC
发明人： Krste Mitric , Qu Gary Jin , Guohui Situ , Paul H.L.M. Schram , Changhui Cathy Zhang , Richard Geiss
IPC分类号： H03L7/07 , H04L5/06 , H03L7/093 , H04J3/16 , H03L7/23 , H03L7/099
CPC分类号： H03L7/07 , H03L7/093 , H03L7/0991 , H03L7/23 , H04L5/06
摘要： A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.
摘要翻译：多通道锁相环（PLL）装置具有多个PLL通道。每个通道包括数字控制振荡器（DCO），通过输出分频器将输出时钟提供给相应的输出引脚。第一个复用器选择任何PLL通道进行对准。反馈校准PLL响应于在相应的输出引脚从所选通道的输出时钟导出的反馈信号。延迟控制模块响应反馈校准PLL的输出来调整输出时钟的相位。

9. 发明申请

US20150326232A1 Crystal Oscillator Noise Compensation Method for a Multi-Loop PLL 有权
标题翻译：多回路PLL晶体振荡器噪声补偿方法
公开(公告)号：US20150326232A1
公开(公告)日：2015-11-12
申请号：US14698966
申请日：2015-04-29
申请人： Microsemi Semiconductor ULC
发明人： Kamran Rahbar , Qu Gary Jin
IPC分类号： H03L7/099 , H03B5/32 , H03L7/093 , H03L7/07
CPC分类号： H03L7/099 , H03B5/32 , H03L7/07 , H03L7/093 , H03L7/0991
摘要： A multi-loop phase locked loop (PLL) system with noise attenuation has a first PLL including a local oscillator, a second PLL coupled to an output of the first PLL, and a third PLL in a feedback path between the second PLL and first PLL. A first phase comparator compares an input signal with the first feedback signal to generate a first phase error signal for the first PLL. The first phase error signal is multiplied by a scaling factor k determining the amount of noise attenuation. The third PLL has a bandwidth preferably at least ten times higher than the second PLL so that the overall transfer function of the second and third PLLs is approximately the transfer function of the second PLL. The transfer function of the third PLL is multiplied by a scaling factor 1/k. This arrangement allows the use of an uncompensated local oscillator in the first PLL. The noise generated in the uncompensated local oscillator is reduced by the attenuation factor k.
摘要翻译：具有噪声衰减的多回路锁相环（PLL）系统具有包括本地振荡器的第一PLL，耦合到第一PLL的输出的第二PLL以及第二PLL和第一PLL之间的反馈路径中的第三PLL 。第一相位比较器将输入信号与第一反馈信号进行比较，以产生用于第一PLL的第一相位误差信号。第一相位误差信号乘以确定噪声衰减量的缩放因子k。第三PLL具有比第二PLL优选至少十倍的带宽，使得第二和第三PLL的总体传递函数近似为第二PLL的传递函数。第三PLL的传递函数乘以缩放因子1 / k。这种布置允许在第一PLL中使用未补偿的本地振荡器。在未补偿的本地振荡器中产生的噪声被衰减因子k减小。

10. 发明授权

US10715307B1 Embedded time of day receiver for clock transmission 有权
公开(公告)号：US10715307B1
公开(公告)日：2020-07-14
申请号：US16563399
申请日：2019-09-06
申请人： Microsemi Semiconductor ULC
发明人： Qu Gary Jin
IPC分类号： H04W4/00 , H04L7/033 , H04J3/02 , H03M13/11 , H04J3/06
摘要： In a receiver a method for extracting first and second signals from a single signal includes receiving the single signal, generating a recovered first signal by extracting and phase locking the first signal with respect to the phase of a local clock, decoding over a decode frame time the data representing an encoded phase difference at the start of the decode frame time, generating a phase difference between the first signal and the second signal as a function of data representing phase difference from a current decode frame time and data representing an encoded phase difference from an immediately prior decode frame time, subtracting the generated phase difference from the phase of the recovered first signal, and generating a recovered second signal by phase locking a signal at the second frequency at the recovered second phase.

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