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1. 发明授权

US10250379B2 Clock recovery device with switchable transient non-linear phase adjuster 有权
公开(公告)号：US10250379B2
公开(公告)日：2019-04-02
申请号：US15701749
申请日：2017-09-12
申请人： Microsemi Semiconductor ULC
发明人： Tariq Haddad , Kamran Rahbar , Peter Meyer
IPC分类号： H03L7/08 , H04J3/06 , H03L7/099 , H04L7/033
摘要： A clock recovery device recovers a master clock over a packet network from incoming synchronization packets. A frequency locked loop generates a control input to a controlled oscillator, which generates an output clock. The frequency locked loop is responsive to pure offset information obtained from the incoming synchronization packets. A transient phase adjuster extracts information from the incoming synchronization packets taking into account transit delays to effect fast frequency adjustment of the control input and to provide a phase adjustment input to the frequency locked loop. A secondary phase path is selectable in response to de-activation of the transient phase adjuster to provide a phase correction to the control input derived from said pure offset information when the transient phase adjuster is inactive.

2. 发明授权

US10069503B2 Method of speeding up output alignment in a digital phase locked loop 有权
公开(公告)号：US10069503B2
公开(公告)日：2018-09-04
申请号：US15597726
申请日：2017-05-17
申请人： Microsemi Semiconductor ULC
发明人： Changhui Cathy Zhang , Qu Gary Jin , Mark A. Warriner , Kamran Rahbar
IPC分类号： H03L7/06 , H03L7/10 , H03L7/18 , H03K5/135 , H03L7/099 , H03L7/091 , H03K5/00
摘要： To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

3. 发明授权

US10003340B2 Multi-format driver interface 有权
公开(公告)号：US10003340B2
公开(公告)日：2018-06-19
申请号：US15653740
申请日：2017-07-19
申请人： Microsemi Semiconductor ULC
发明人： Chi Yu Lung
IPC分类号： H03K19/0185 , H03K19/0175 , H03K17/693 , H03K19/094 , G06F13/368 , H03K17/687 , H03K5/134
CPC分类号： H03K19/018571 , G06F13/368 , H03K5/134 , H03K17/6871 , H03K19/017518 , H03K19/018521 , H03K19/018585 , H03K19/09429 , H03K2217/0018 , Y02D10/14
摘要： A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second transistors of the first and second pairs of transistors form respective first and second parallel arrangement. The first transistors of the third pair of transistors are in series with the first parallel arrangement, and the second transistors of the third pair of transistors are in series with the second parallel arrangement. The sizing of the second pair of transistors is greater than the first and third pairs of transistors. A pre-driver module configures the multi-format signal driver interface to output a selected signal format. A differential amplifier is selectively couple-able to said pre-driver module to provide a common mode voltage. In each format the interface employs a current loop in the output. The transistor pairs are one-to-one loaded in each mode.

4. 发明申请

US20180048312A1 MULTI-FORMAT DRIVER INTERFACE 有权
公开(公告)号：US20180048312A1
公开(公告)日：2018-02-15
申请号：US15653740
申请日：2017-07-19
申请人： Microsemi Semiconductor ULC
发明人： Chi Yu Lung
IPC分类号： H03K19/0185 , G06F13/368 , H03K17/687 , H03K5/134 , H03K19/094 , H03K19/0175
CPC分类号： H03K19/018571 , G06F13/368 , H03K5/134 , H03K17/6871 , H03K19/017518 , H03K19/018521 , H03K19/018585 , H03K19/09429 , H03K2217/0018
摘要： A multi-format signal driver interface has first, second and third pairs of transistors arranged in a back-to-back relationship. First transistors and second transistors of the first and second pairs of transistors form respective first and second parallel arrangement. The first transistors of the third pair of transistors are in series with the first parallel arrangement, and the second transistors of the third pair of transistors are in series with the second parallel arrangement. The sizing of the second pair of transistors is greater than the first and third pairs of transistors. A pre-driver module configures the multi-format signal driver interface to output a selected signal format. A differential amplifier is selectively couple-able to said pre-driver module to provide a common mode voltage. In each format the interface employs a current loop in the output. The transistor pairs are one-to-one loaded in each mode.

5. 发明申请

US20170093410A1 NOISE REDUCTION IN NON-LINEAR SIGNAL PROCESSING 有权
公开(公告)号：US20170093410A1
公开(公告)日：2017-03-30
申请号：US15278187
申请日：2016-09-28
申请人： Microsemi Semiconductor ULC
发明人： Foad Arfaei Malekzadeh , Mehran Aliahmad
IPC分类号： H03L7/099 , H03M3/00
CPC分类号： H03L7/0991 , G06F1/022 , H03M3/328 , H03M3/424 , H03M3/50
摘要： A method for reducing the jitter introduced into a digital signal by a non-linear processing element involves applying an input word representing the digital signal to a first signal path comprising a first non-linear processing element, and a complementary version of the input word to a second signal path comprising a second non-linear processing element. A common mode dither signal is injected into each signal path upstream of the non-linear processing elements. The outputs of the non-linear processing elements are combined to produce a common output with the common mode dither signal removed.

6. 发明授权

US09503254B2 Phase locked loop with modified loop filter 有权
标题翻译：带有修正环路滤波器的锁相环
公开(公告)号：US09503254B2
公开(公告)日：2016-11-22
申请号：US14930797
申请日：2015-11-03
申请人： MICROSEMI SEMICONDUCTOR ULC
发明人： Kamran Rahbar , Peter Crosby
IPC分类号： H03D3/24 , H04L7/033 , H03L7/00 , H04J3/06 , H03L7/093
CPC分类号： H04L7/0331 , H03L7/00 , H03L7/093 , H04J3/0697
摘要： A loop filter in a modified phase locked loop has a proportional path generating first output signal that is proportional to an input signal and an integral path for generating a second output signal that is an integral of the input signal. An additional functional path generates a third output signal that is a predetermined function of the input signal. The predetermined function is of the form f(s)/g(s), where f and g are polynomial functions. An adder combines the first, second, and third output signals into a common output signal.
摘要翻译：经修改的锁相环中的环路滤波器具有产生与输入信号成比例的第一输出信号的比例路径和用于产生作为输入信号的积分的第二输出信号的积分路径。附加功能路径产生作为输入信号的预定功能的第三输出信号。预定函数的形式为f（s）/ g（s），其中f和g是多项式函数。加法器将第一，第二和第三输出信号组合成公共输出信号。

7. 发明申请

US20160301419A1 Apparatus for Generating Clock Signals having a PLL part and Synthesizer Part with Programmable Output Dividers 有权
标题翻译：用于产生具有PLL部分的时钟信号和具有可编程输出分频器的合成器部分的装置
公开(公告)号：US20160301419A1
公开(公告)日：2016-10-13
申请号：US15091993
申请日：2016-04-06
申请人： Microsemi Semiconductor ULC
发明人： Paul H.L.M. Schram , Krste Mitric , Gabriel Rusaneanu
IPC分类号： H03L7/181 , H03L7/099
CPC分类号： H03L7/16 , G06F1/12 , H03B19/00
摘要： A clock signal generator responsive to synchronization pulses to perform actions has a phase locked loop (PLL) part including a digitally controlled oscillator (DCO) and an output driver coupled to the DCO, and a synthesizer part including a frequency synthesizer responsive to frequency and phase information from the DCO to generate a synthesized clock and programmable output dividers for generating output clocks from the synthesized clock. An interface establishes communication between the PLL part and the synthesizer part. The output driver is programmed to compute a phase offset required to align a selected output divider with the phase of the DCO and transmit the computed offset to the selected output divider over said interface for application to said selected output divider upon the occurrence of a synchronization pulse.
摘要翻译：响应于同步脉冲以执行动作的时钟信号发生器具有包括耦合到DCO的数字控制振荡器（DCO）和输出驱动器的锁相环（PLL）部分，以及包括响应于频率和相位的频率合成器的合成器部分来自DCO的信息以产生合成时钟和可编程输出分频器，用于从合成时钟产生输出时钟。接口建立PLL部分和合成器部分之间的通信。输出驱动器被编程为计算将所选择的输出分频器与DCO的相位对准所需的相位偏移，并且通过所述接口将所计算的偏移量传送到所选择的输出分频器，以在发生同步脉冲时应用于所述选择的输出分频器。

8. 发明申请

US20160301416A1 Digital Phase Locked Loop Arrangement with Master Clock Redundancy 有权
标题翻译：数字锁相环布置与主时钟冗余
公开(公告)号：US20160301416A1
公开(公告)日：2016-10-13
申请号：US15064678
申请日：2016-03-09
申请人： Microsemi Semiconductor ULC
发明人： Slobodan Milijevic , Johannes Hermanus Aloysius de Rijk , Paul H.L.M. Schram , Mark A. Warriner
IPC分类号： H03L7/07 , H03L7/099
CPC分类号： H03L7/07 , H03L7/14 , H03L2207/50
摘要： Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.
摘要翻译：为具有由主时钟源（例如，晶体振荡器）驱动的数字控制振荡器（DCO）的数字锁相环提供主时钟冗余。选择产生时钟信号的多个晶体振荡器中的一个来驱动DCO。监视晶体振荡器的性能，并且当从先前选择的晶体振荡器丢失时钟信号时，或者当先前选择的晶体的性能失去时，DCO从先前选择的晶体振荡器切换到新选择的晶体振荡器振荡器低于预定的可接受水平。

9. 发明申请

US20160294401A1 Hardware Delay Compensation in Digital Phase Locked Loop 有权
标题翻译：数字锁相环硬件延迟补偿
公开(公告)号：US20160294401A1
公开(公告)日：2016-10-06
申请号：US15064663
申请日：2016-03-09
申请人： Microsemi Semiconductor ULC
发明人： Qu Gary Jin , Paul H.L.M. Schram , Krste Mitric , Cathy Zhang , Gabriel Rusaneanu , Wenbao Wang
IPC分类号： H03L7/099 , H03L7/07 , H03K5/135 , H03L7/093
CPC分类号： H03K5/135 , H03K2005/00104 , H03L7/07 , H03L7/0805 , H03L7/081 , H03L7/085 , H03L7/093 , H03L2207/50
摘要： In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.
摘要翻译：在包括响应于控制值的第一软件实现的受控振荡器（SDCO）的PLL环路的数字锁相环中，以产生锁定到参考输入信号的输出相位和频率值，以及响应于输出的硬件实现的受控振荡器来自所述第一SDCO的相位和频率值以合成所述时钟信号，通过对所述合成时钟信号或其派生进行采样来补偿硬件延迟，以产生合成时钟相位值。将合成的时钟信号相位值与从PLL环路导出的反馈相位值进行比较，以产生修正合成时钟信号或其导数的补偿值。

10. 发明授权

US09444470B2 Double phase-locked loop with frequency stabilization 有权
标题翻译：具有频率稳定的双锁相环
公开(公告)号：US09444470B2
公开(公告)日：2016-09-13
申请号：US14595309
申请日：2015-01-13
申请人： MICROSEMI SEMICONDUCTOR ULC
发明人： Slobodan Milijevic
IPC分类号： H03L7/06 , H03L7/087 , H03L7/099 , H03L7/07 , H03L7/08 , H03L7/22
CPC分类号： H03L7/087 , H03L7/07 , H03L7/0805 , H03L7/0807 , H03L7/0991 , H03L7/22
摘要： A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks.
摘要翻译：双锁相具有第一锁相环，其包括被配置为减少第一输入时钟中的相位噪声的第一窄带环路滤波器和包括第二环路滤波器的第二锁相环，该第二环路滤波器被配置为从第一输入时钟接收第二输入时钟稳定的时钟源。第二个时钟具有接近所述第一时钟的频率。第一个循环的带宽至少比第二个循环要小一个数量级。耦合器耦合第一和第二锁相环以提供公共输出。例如，双锁相环可以用于在无线网络中提供时刻信息，或者用作从电信/数据通信网络恢复的时钟信号中清除相位噪声的精细滤波器。

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