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1. 发明授权

US10270451B2 Low leakage ReRAM FPGA configuration cell 有权
公开(公告)号：US10270451B2
公开(公告)日：2019-04-23
申请号：US15375014
申请日：2016-12-09
申请人： Microsemi SoC Corporation
发明人： John L. McCollum , Esmat Z. Hamdy
IPC分类号： G11C13/00 , H03K19/094 , H01L27/24 , H01L23/00 , H03K19/177 , H01L45/00
摘要： A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.

2. 发明授权

US09444464B1 Compact ReRAM based FPGA 有权
标题翻译：紧凑型基于ReRAM的FPGA
公开(公告)号：US09444464B1
公开(公告)日：2016-09-13
申请号：US15010222
申请日：2016-01-29
申请人： Microsemi SoC Corporation
发明人： John L. McCollum , Fethi Dhaoui
IPC分类号： G11C11/00 , H03K19/177 , G11C13/00
CPC分类号： H01L27/2454 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2213/82 , H01L21/768 , H01L45/16 , H03K19/1776
摘要： A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
摘要翻译：推挽电阻随机存取存储器单元电路包括输出节点，字线，第一位线和第二位线。第一电阻随机存取存储器件连接在第一位线和输出节点之间，第二电阻随机存取存储器件连接在输出节点和第二位线之间。第一编程晶体管具有连接到字线的栅极，连接到输出节点的漏极和源极。第二编程晶体管具有连接到字线的栅极，连接到第一编程晶体管的源极的漏极和源极。第一和第二编程晶体管具有相同的间距，相同的沟道长度和相同的栅介质厚度，选择栅极电介质厚度以承受在推挽式ReRAM单元电路的操作期间遇到的编程和擦除电位。

3. 发明授权

US09991894B2 Resistive random access memory cells 有权
公开(公告)号：US09991894B2
公开(公告)日：2018-06-05
申请号：US14835928
申请日：2015-08-26
申请人： Microsemi SoC Corporation
发明人： Jonathan Greene , Frank Hawley , John L. McCollum
IPC分类号： H03K19/177 , H01L27/24 , H01L45/00
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A layout arrangement for a resistive random access memory cell includes an active area, a polysilicon row address line over the active region, a metal column address line running orthogonal to the row address line and having an active region contact portion extending over the active region and having a contact to the active region. A metal output line runs parallel to the column address line over the active region. A first cell contact region intersects with the output line and has a contact to the active region. A first metal cell contact region forms an intersection with the first cell contact region. A first resistive random access memory device is formed at the intersection of the first cell contact region and the output line. A second resistive random access memory device is formed at the intersection of the first cell contact region and the first cell contact region.

4. 发明授权

US09990993B2 Three-transistor resistive random access memory cells 有权
公开(公告)号：US09990993B2
公开(公告)日：2018-06-05
申请号：US15375036
申请日：2016-12-09
申请人： Microsemi SoC Corporation
发明人： John L. McCollum , Volker Hecht
IPC分类号： G11C11/00 , G11C13/00 , H01L27/24
CPC分类号： G11C13/0069 , G11C13/003 , G11C2013/0042 , G11C2213/74 , G11C2213/79 , H01L27/2436
摘要： A ReRAM cell array has having at least one row and one column includes first and second complementary bit lines for each row, a word line, a p-word line, and an n-word line for each column. A ReRAM cell at each row and column of the array includes a first ReRAM device, its first end connected to the first complementary bit line of its row, a p-channel transistor, its source connected to a second end of the first ReRAM device, its drain connected to a switch node, its gate connected to the p-channel word line of its column, a second ReRAM device, its first end connected to the second complementary bit line of its row, an n-channel transistor, its source connected to a second end of the second ReRAM device, its drain connected to the switch node, its gate connected to the n-channel word line of its column.

5. 发明授权

US09484904B2 Gate boosting transmission gate 有权
标题翻译：门增压传输门
公开(公告)号：US09484904B2
公开(公告)日：2016-11-01
申请号：US14703720
申请日：2015-05-04
申请人： Microsemi SoC Corporation
发明人： John L. McCollum
IPC分类号： H03K17/687 , H03K17/0412 , H01L27/092
CPC分类号： H03K17/04123 , H01L27/0922 , H03K17/6872 , H03K2217/0054
摘要： A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold.
摘要翻译：门升压传输门包括输入节点和输出节点。 n沟道晶体管具有连接到输入节点的第一源极/漏极端子和连接到输出节点的第二源极/漏极端子，n沟道晶体管具有低阈值。 p沟道晶体管具有连接到输入节点的第一源极/漏极端子和连接到输出节点的第二源极/漏极端子，p沟道晶体管具有非常低的阈值。

6. 发明申请

US20160204223A1 HIGH VOLTAGE DEVICE FABRICATED USING LOW-VOLTAGE PROCESSES 审中-公开
标题翻译：使用低电压工艺制造的高压器件
公开(公告)号：US20160204223A1
公开(公告)日：2016-07-14
申请号：US15075972
申请日：2016-03-21
申请人： Microsemi SoC Corporation
发明人： Fengliang Xue , Fethi Dhaoui , John L. McCollum
IPC分类号： H01L29/66 , H01L21/265
CPC分类号： H01L29/66492 , H01L21/265 , H01L29/0653 , H01L29/0847 , H01L29/665 , H01L29/7833 , H01L29/7835
摘要： A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.
摘要翻译：在半导体衬底上制造高电压晶体管的方法包括限定和形成用于所有晶体管的浅沟槽隔离区，为所有晶体管限定和形成阱区，在阱区中形成用于所有晶体管的栅极氧化物层所述晶体管在所述栅极氧化物层上形成所有晶体管的栅极，注入掺杂剂以形成所有所述晶体管的轻掺杂漏极区，所述高电压晶体管的至少漏极的所述轻掺杂漏极区间隔开除了浅沟槽隔离区域的内边缘之外，在所有晶体管的栅极的侧面形成栅极间隔物，并且注入掺杂剂以形成所有晶体管的源极和漏极，高压晶体管的漏极为完全被高电压晶体管的轻掺杂漏区包围。

7. 发明申请

US20150365090A1 RESISTIVE RANDOM ACCESS MEMORY CELLS 有权
公开(公告)号：US20150365090A1
公开(公告)日：2015-12-17
申请号：US14835928
申请日：2015-08-26
申请人： Microsemi SoC Corporation
发明人： Jonathan Greene , Frank Hawley , John L. McCollum
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A layout arrangement for a resistive random access memory cell includes an active area, a polysilicon row address line over the active region, a metal column address line running orthogonal to the row address line and having an active region contact portion extending over the active region and having a contact to the active region. A metal output line runs parallel to the column address line over the active region. A first cell contact region intersects with the output line and has a contact to the active region. A first metal cell contact region forms an intersection with the first cell contact region. A first resistive random access memory device is formed at the intersection of the first cell contact region and the output line. A second resistive random access memory device is formed at the intersection of the first cell contact region and the first cell contact region.

8. 发明申请

US20180090205A1 THREE-TRANSISTOR RESISTIVE RANDOM ACCESS MEMORY CELLS 有权
公开(公告)号：US20180090205A1
公开(公告)日：2018-03-29
申请号：US15375036
申请日：2016-12-09
申请人： Microsemi SoC Corporation
发明人： John L. McCollum , Volker Hecht
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/0069 , G11C13/003 , G11C2013/0042 , G11C2213/74 , G11C2213/79 , H01L27/2436
摘要： A ReRAM cell array has having at least one row and one column includes first and second complementary bit lines for each row, a word line, a p-word line, and an n-word line for each column. A ReRAM cell at each row and column of the array includes a first ReRAM device, its first end connected to the first complementary bit line of its row, a p-channel transistor, its source connected to a second end of the first ReRAM device, its drain connected to a switch node, its gate connected to the p-channel word line of its column, a second ReRAM device, its first end connected to the second complementary bit line of its row, an n-channel transistor, its source connected to a second end of the second ReRAM device, its drain connected to the switch node, its gate connected to the n-channel word line of its column.

9. 发明申请

US20160269031A1 COMPACT ReRAM BASED FPGA 有权
标题翻译：基于ReRAM的FPGA
公开(公告)号：US20160269031A1
公开(公告)日：2016-09-15
申请号：US15010222
申请日：2016-01-29
申请人： Microsemi SoC Corporation
发明人： John L. McCollum , Fethi Dhaoui
IPC分类号： H03K19/177 , G11C13/00
CPC分类号： H01L27/2454 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2213/82 , H01L21/768 , H01L45/16 , H03K19/1776
摘要： A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
摘要翻译：推挽电阻随机存取存储器单元电路包括输出节点，字线，第一位线和第二位线。第一电阻随机存取存储器件连接在第一位线和输出节点之间，第二电阻随机存取存储器件连接在输出节点和第二位线之间。第一编程晶体管具有连接到字线的栅极，连接到输出节点的漏极和源极。第二编程晶体管具有连接到字线的栅极，连接到第一编程晶体管的源极的漏极和源极。第一和第二编程晶体管具有相同的间距，相同的沟道长度和相同的栅介质厚度，选择栅极电介质厚度以承受在推挽式ReRAM单元电路的操作期间遇到的编程和擦除电位。

10. 发明授权

US09306573B2 Apparatus and method for detecting and preventing laser interrogation of an FPGA integrated circuit 有权
标题翻译：用于检测和防止FPGA集成电路的激光询问的装置和方法
公开(公告)号：US09306573B2
公开(公告)日：2016-04-05
申请号：US14790982
申请日：2015-07-02
申请人： Microsemi SoC Corporation
发明人： John L. McCollum
IPC分类号： H03K19/177
CPC分类号： H03K19/17768
摘要： A circuit internal to a programmable integrated circuit for preventing laser interrogation of the programmable integrated circuit includes a sense resistor connected between a deep n-well and a source of bias voltage for the deep n-well. A voltage-sensing circuit is coupled across the sense resistor to measure voltage across the sense resistor. A tamper trigger circuit responsive to the voltage sensing circuit generates a tamper signal in response to a voltage sensed in the voltage sensing circuit having a magnitude greater than a threshold value.
摘要翻译：用于防止可编程集成电路的激光询问的可编程集成电路内部的电路包括连接在深n阱和深n阱的偏置电压源的检测电阻器。电压感测电路耦合在检测电阻器两端以测量检测电阻器两端的电压。响应于电压感测电路的篡改触发电路响应于具有大于阈值的电压感测电路中检测到的电压而产生篡改信号。

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