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1. 发明授权

US10270451B2 Low leakage ReRAM FPGA configuration cell 有权
公开(公告)号：US10270451B2
公开(公告)日：2019-04-23
申请号：US15375014
申请日：2016-12-09
申请人： Microsemi SoC Corporation
发明人： John L. McCollum , Esmat Z. Hamdy
IPC分类号： G11C13/00 , H03K19/094 , H01L27/24 , H01L23/00 , H03K19/177 , H01L45/00
摘要： A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.

2. 发明授权

US10243572B2 Hybrid phase locked loop having wide locking range 有权
公开(公告)号：US10243572B2
公开(公告)日：2019-03-26
申请号：US15364167
申请日：2016-11-29
申请人： Microsemi SoC Corporation
发明人： Prakash Reddy
IPC分类号： H03L7/00 , H03L7/10 , H03L7/087 , H03L7/093 , H03L7/099
摘要： A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at an output signal frequency, and a phase comparator configured to compare the output signal or a signal derived from the output signal, with a reference signal at a reference signal frequency or a signal derived from the reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator. A frequency error measuring circuit produces a frequency error signal that directly represents a frequency difference between the output signal frequency and the reference signal frequency. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and providing the combined control signals to the digital controlled oscillator.

3. 发明授权

US09953166B2 Method for securely booting target processor in target system using a secure root of trust to verify a returned message authentication code recreated by the target processor 有权
公开(公告)号：US09953166B2
公开(公告)日：2018-04-24
申请号：US14322953
申请日：2014-07-03
申请人： Microsemi SoC Corporation
发明人： G. Richard Newell
IPC分类号： G06F9/00 , G06F15/177 , G06F21/57 , G06F21/44
CPC分类号： G06F21/575 , G06F21/44 , G06F2221/2103
摘要： A method for securely booting a target processor in a target system from a secure root of trust includes computing a message authentication code from boot code to be provided to the target processor, including an obfuscated algorithm for recreating the message authentication code in the target processor, serving the boot code to the target processor, executing the boot code to recreate the message authentication code in the target processor, serving the message authentication code back to the root of trust, comparing the returned message authentication code with the message authentication code generated in the root of trust, continuing execution of the boot code data if the returned message authentication code matches the message authentication code, and applying at least one penalty to the target system if the returned message authentication code does not match the message authentication code generated in the root of trust.

4. 发明授权

US09704573B1 Three-transistor resistive random access memory cells 有权
公开(公告)号：US09704573B1
公开(公告)日：2017-07-11
申请号：US15375046
申请日：2016-12-09
申请人： Microsemi SoC Corporation
发明人： Volker Hecht
IPC分类号： G11C11/00 , G11C13/00 , H01L27/24 , H01L23/528
CPC分类号： G11C13/0069 , G11C11/1659 , G11C13/0028 , G11C13/003 , G11C13/0097 , G11C2013/0078 , G11C2213/74 , G11C2213/78 , G11C2213/79 , H01L23/528 , H01L27/2436 , H01L27/2463
摘要： A pair of adjacent ReRAM cells in an array includes a first bit line for a row of the array, a second bit line for the row of the array, a p-channel word line associated with two adjacent columns in the array, and an n-channel word line associated with the two adjacent columns. A pair of ReRAM cells in the adjacent columns in the row each includes a switch node, a first ReRAM device connected between the first bit line and the source of a p-channel transistor. The drain of the p-channel transistor is connected to the switch node, and its gate is connected to the p-channel word line. A second ReRAM device is connected between the second bit line and the source of an n-channel transistor. The drain of the n-channel transistor is connected to the switch node, and its gate is connected to the n-channel word line.

5. 发明授权

US09444464B1 Compact ReRAM based FPGA 有权
标题翻译：紧凑型基于ReRAM的FPGA
公开(公告)号：US09444464B1
公开(公告)日：2016-09-13
申请号：US15010222
申请日：2016-01-29
申请人： Microsemi SoC Corporation
发明人： John L. McCollum , Fethi Dhaoui
IPC分类号： G11C11/00 , H03K19/177 , G11C13/00
CPC分类号： H01L27/2454 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/78 , G11C2213/79 , G11C2213/82 , H01L21/768 , H01L45/16 , H03K19/1776
摘要： A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.
摘要翻译：推挽电阻随机存取存储器单元电路包括输出节点，字线，第一位线和第二位线。第一电阻随机存取存储器件连接在第一位线和输出节点之间，第二电阻随机存取存储器件连接在输出节点和第二位线之间。第一编程晶体管具有连接到字线的栅极，连接到输出节点的漏极和源极。第二编程晶体管具有连接到字线的栅极，连接到第一编程晶体管的源极的漏极和源极。第一和第二编程晶体管具有相同的间距，相同的沟道长度和相同的栅介质厚度，选择栅极电介质厚度以承受在推挽式ReRAM单元电路的操作期间遇到的编程和擦除电位。

6. 发明申请

US20160180922A1 MULTI-STATE CONFIGURATION RAM CELL 有权
标题翻译：多状态配置RAM单元
公开(公告)号：US20160180922A1
公开(公告)日：2016-06-23
申请号：US14950114
申请日：2015-11-24
申请人： Microsemi SoC Corporation
发明人： Jonathan W. Greene
IPC分类号： G11C11/412 , G11C5/06 , G11C11/418
CPC分类号： G11C11/412 , G11C5/063 , G11C11/418 , G11C11/56
摘要： A multi-state static RAM cell includes N NOR gates. Each NOR gate has N-1 inputs and one output. The output of each NOR gate is coupled to a different bit line. Each NOR gate has its inputs connected to the outputs of each of the other NOR gates.
摘要翻译：多状态静态RAM单元包括N个或非门。每个或非门都有N-1个输入和一个输出。每个或非门的输出耦合到不同的位线。每个或非门都有其输入连接到每个其他NOR门的输出。

7. 发明申请

US20150370247A1 IDENTIFYING INTEGRATED CIRCUIT ORIGIN USING TOOLING SIGNATURE 审中-公开
标题翻译：使用工具识别识别集成电路原点
公开(公告)号：US20150370247A1
公开(公告)日：2015-12-24
申请号：US14747758
申请日：2015-06-23
申请人： Microsemi SoC Corporation
发明人： G. Richard Newell , Russell Robert Garcia
IPC分类号： G05B19/418
CPC分类号： G05B19/41875 , G05B2219/32222 , Y02P90/22
摘要： A method for determining if an individual integrated circuit was manufactured using an individual instance of tooling includes collecting from the individual integrated circuit first data representing at least one attribute that varies as a function of the tooling used to manufacture the individual integrated circuit and second data identifying the integrated circuit as having been manufactured using the individual instance of tooling. The first data is compared to a signature of the individual instance of tooling identified by the second data. The signature is derived from the at least one attribute measured from a population of integrated circuits that were manufactured using the individual instance of tooling. The individual integrated circuit is identified as having been manufactured using the individual instance of tooling identified in the second data collected from the individual integrated circuit if the first data correlates to the signature by a predetermined threshold.
摘要翻译：用于确定单个集成电路是否使用单个工具实例来制造的方法包括从各个集成电路收集首先表示至少一个属性的数据，所述属性随着用于制造单个集成电路的工具而变化，并且第二数据识别集成电路已经使用工具的单独实例制造。将第一数据与由第二数据标识的工具的单个实例的签名进行比较。签名是从使用个别工具实例制造的集成电路群体测量的至少一个属性导出的。如果第一数据与签名相关联的预定阈值，则将个体集成电路识别为已经使用从单个集成电路收集的第二数据中标识的工具的单独实例来制造。

8. 发明申请

US20150084670A1 SONOS FPGA Architecture Having Fast Data Erase and Disable Feature 有权
标题翻译： SONOS FPGA架构具有快速数据擦除和禁用功能
公开(公告)号：US20150084670A1
公开(公告)日：2015-03-26
申请号：US14481943
申请日：2014-09-10
申请人： Microsemi SoC Corporation
发明人： John McCollum
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , G06F12/14 , G06F21/76 , H03K19/17752 , H03K19/1776 , H03K19/17772
摘要： A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, which includes detecting tampering with the FPGA, disconnecting power from the programmable logic core, and simultaneously programming the n-channel device and erasing the p-channel device in all cells.
摘要翻译：一种用于快速数据擦除FPGA的方法，包括由多个SONOS配置存储器单元控制的可编程逻辑核，每个SONOS配置存储单元包括与n沟道SONOS存储晶体管串联的p沟道SONOS存储晶体管，其包括检测篡改FPGA，断开与可编程逻辑内核的电源，同时编程n通道器件并擦除所有单元中的p沟道器件。

9. 发明申请

US20140269133A1 Background Auto-refresh Apparatus and Method for Non-Volatile Memory Array 有权
标题翻译：背景自动刷新装置和非易失性存储器阵列的方法
公开(公告)号：US20140269133A1
公开(公告)日：2014-09-18
申请号：US14208513
申请日：2014-03-13
申请人： Microsemi SoC Corporation
发明人： John McCollum
IPC分类号： G11C11/406
CPC分类号： H03K19/1776 , G11C11/23 , G11C16/3431
摘要： A method for automatically refreshing a non-volatile memory array in the background without memory interruption includes selecting an unrefreshed segment of the memory, reading data from each row in the selected segment during memory dead time and storing the data read from each row in a local temporary storage memory until an entire segment is read out, remapping all memory addresses in the selected segment to the temporary storage memory, isolating column lines in the selected segment from global column lines, erasing the data in the selected segment without disturbing the column lines, rewriting memory data in each row of the selected segment, remapping all memory addresses in the selected segment to the memory, and repeating the process until all segments have been refreshed.
摘要翻译：用于在没有存储器中断的情况下自动刷新背景中的非易失性存储器阵列的方法包括选择存储器的未刷新段，在存储器死区时间期间从所选段中的每一行读取数据，并将从每行读取的数据存储在本地临时存储器，直到读出整个段，将所选段中的所有存储器地址重新映射到临时存储器，将所选段中的列与全局列线隔离，擦除所选段中的数据而不干扰列线，重写所选段的所有存储器地址到存储器，并重复该过程，直到所有段被刷新。

10. 发明申请

US20130271180A1 FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES 有权
标题翻译： FPGA RAM块优化用作寄存器文件
公开(公告)号：US20130271180A1
公开(公告)日：2013-10-17
申请号：US13898827
申请日：2013-05-21
申请人： Microsemi SoC Corporation
发明人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , G11C8/16 , H03K19/1776
摘要： A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
摘要翻译：公开了一种适用于现场可编程门阵列集成电路器件的随机存取存储器电路。 FPGA具有可编程阵列，其具有逻辑模块和路由互连，可编程地耦合到逻辑模块和RAM电路。 RAM电路具有三个端口：第一可读端口，第二可读端口和可写入端口。读端口可以是可编程同步的或异步的，并且具有可编程可旁路输出流水线寄存器。 RAM电路特别适用于实现寄存器文件。还描述了一种新颖的互连方法。

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