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1. 发明申请

US20080024180A1 DELAY LOCKED LOOP CIRCUITS AND METHODS OF GENERATING CLOCK SIGNALS 有权
标题翻译：延迟锁定环路和产生时钟信号的方法
公开(公告)号：US20080024180A1
公开(公告)日：2008-01-31
申请号：US11761464
申请日：2007-06-12
申请人： Moon-Sook PARK , Young-Don CHOI
发明人： Moon-Sook PARK , Young-Don CHOI
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/10 , H03L7/189
摘要： A delay locked loop circuit includes a phase detector configured to compare a phase of a reference clock signal with a phase of an output clock signal and to output a comparison signal, a control voltage generator configured to output a control voltage based on the comparison signal, a voltage controlled delay line comprising a plurality of delay elements and configured to delay the reference clock signal based on the control voltage and to output the output clock signal, and a control voltage initializer configured to generate digital codes based on characteristics of the voltage controlled delay line and to generate an initial control voltage based on the digital codes.
摘要翻译：延迟锁定环电路包括：相位检测器，被配置为将参考时钟信号的相位与输出时钟信号的相位进行比较并输出比较信号;控制电压发生器，被配置为基于比较信号输出控制电压; 电压控制延迟线，包括多个延迟元件，并且被配置为基于所述控制电压延迟所述参考时钟信号并输出所述输出时钟信号;以及控制电压初始化器，被配置为基于所述电压控制延迟的特性生成数字代码并基于数字代码产生初始控制电压。

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