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1. 发明公开

US20230412175A1 CONTROL AND CALIBRATION OF EXTERNAL OSCILLATORS 审中-公开
公开(公告)号：US20230412175A1
公开(公告)日：2023-12-21
申请号：US18247691
申请日：2021-12-07
申请人： Analog Devices, Inc.
发明人： Hyman Shanan , John Kenney
IPC分类号： H03L7/099 , H03L1/02 , H03L7/189 , H04B1/16
CPC分类号： H03L7/099 , H03L1/02 , H03L7/189 , H04B1/16 , H03L2207/06
摘要： Apparatus and methods for control and calibration of external oscillators are provided herein. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator that is external to the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.

2. 发明公开

US20230353160A1 ANALOG TRACKING CIRCUIT TO IMPROVE DYNAMIC AND STATIC IMAGE REJECTION OF A FREQUENCY CONVERTER 审中-公开
公开(公告)号：US20230353160A1
公开(公告)日：2023-11-02
申请号：US17732099
申请日：2022-04-28
申请人： Analog Devices International Unlimited Company
发明人： Justin L. FORTIER , Christopher W. ANGELL , David J. MCLAURIN , Oscar S. BURBANO , Ionel GHEORGHE , Mostafa HAROUN , Xing ZHOU
IPC分类号： H03L7/189 , H03L7/193 , H03K23/40 , H03K21/40
CPC分类号： H03L7/189 , H03L7/193 , H03K23/40 , H03K21/40 , H04B1/0096
摘要： Systems, devices, and methods related to frequency converter arrangements are provided. For example, a frequency converter arrangement converts a first signal centered at a first frequency to a second signal centered at a second frequency different from the first frequency. The frequency converter arrangement includes local oscillator (LO) circuitry and in-phase, quadrature-phase (IQ) mixer circuitry coupled to the LO circuitry. The LO circuitry includes duty cycle correction circuitry to adjust a duty cycle of a pair of input clock signals. The duty cycle correction circuitry includes coarse tuning circuitry responsive to a digital calibration code, and analog tuning loop circuitry. The LO circuitry further includes quadrature divider circuitry coupled to an output of the duty cycle correction circuitry, where the quadrature divider circuitry generates an in-phase LO signal and a quadrature-phase LO signal from a pair of output clock signals at outputs of the duty cycle correction circuitry.

3. 发明申请

US20190052227A1 METHOD FOR THE FREQUENCY CORRECTION OF AN OSCILLATOR OF A SENSOR NODE OF A WIRELESS SENSOR NETWORK 审中-公开
公开(公告)号：US20190052227A1
公开(公告)日：2019-02-14
申请号：US16076539
申请日：2017-02-15
申请人： Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. , Friedrich-Alexander-Univerität Erlangen-Nürnberg
发明人： Hans-Martin Tröger , Norbert Franke , Albert Heuberger , Jörg Robert
IPC分类号： H03D3/00 , H04L27/26 , H03L7/189
CPC分类号： H03D3/004 , H03L7/189 , H04L27/2657 , H04L27/2675 , H04L27/2695
摘要： The invention relates to a method for the frequency error correction of an oscillator of a sensor node in a sensor network, comprising the following steps: receiving a transmission signal of a transmitter, the signal being modulated by orthogonal frequency division multiplexing (OFDM); determining the frequency deviation of the oscillator using the received transmission signal; determining a correction signal for correcting the frequency deviation of the oscillator and correcting the frequency of the oscillator by means of the correction signal.

4. 发明授权

US10063245B2 Reference signal generator 有权
公开(公告)号：US10063245B2
公开(公告)日：2018-08-28
申请号：US15533957
申请日：2015-11-10
申请人： Furuno Electric Co., Ltd.
发明人： Kunihiko Hashimoto
IPC分类号： H03L7/099 , H03L7/091 , H04L7/04
CPC分类号： H03L7/0992 , H03L7/0805 , H03L7/0807 , H03L7/091 , H03L7/14 , H03L7/143 , H03L7/189 , H04L7/0029 , H04L7/0331 , H04L7/04
摘要： In a reference signal generator including a synchronization circuit configured to convert a digital signal into an analog signal, supply this signal to a voltage controlled oscillator, and control the voltage controlled oscillator to obtain a signal synchronized with the reference signal, without an accumulation of quantization error in a holdover control in which an acquisition of a reference signal is not available. The reference signal generator includes a phase synchronization circuit and a controller. The phase synchronization circuit controls the reference signal outputted from the oscillator, according to a control signal obtained based on the reference signal. The controller generates a free-running control signal and controls the oscillator when the reference signal becomes unavailable. The oscillator receives discrete values and oscillates accordingly. A digital delta-sigma modulator configured to modulate the free-running control signal of the controller is disposed in a subsequent stage of the controller.

5. 发明申请

US20180097521A1 Method and Apparatus for Calibration of Voltage Controlled Oscillator 审中-公开
公开(公告)号：US20180097521A1
公开(公告)日：2018-04-05
申请号：US15676080
申请日：2017-08-14
申请人： Apple Inc.
发明人： Joachim S. Hammerschmidt , Robert G. Lorenz
IPC分类号： H03L7/089 , H03C3/09 , H03L7/099 , H03L7/10 , H03L7/18
CPC分类号： H03L7/0893 , H03B5/1243 , H03B5/1265 , H03B2201/025 , H03B2201/0266 , H03C3/0925 , H03C3/0933 , H03C3/095 , H03C3/0958 , H03C3/0991 , H03J2200/10 , H03L7/0805 , H03L7/0996 , H03L7/104 , H03L7/105 , H03L7/18 , H03L7/189 , H03L2207/06
摘要： A method and apparatus for performing a two-point calibration of a VCO in a PLL is disclosed. The method includes determining a first steady state tuning voltage of the VCO with no modulation voltage applied. Thereafter, an iterative process may be performed wherein a modulation voltage is applied to the VCO (along with the tuning voltage) and a modified divisor is applied to the divider circuit in the feedback loop. During each iteration, after the PLL is settled, the tuning voltage is measured and a difference between the current value and the first value is determined. If the current and first values of the turning voltage are not equal, another iteration may be performed, modifying at least one of the modulation voltage and the divisor, and determining the difference between the current and first values of the tuning voltage.

6. 发明授权

US08552773B2 Phase locked loop 有权
标题翻译：锁相环
公开(公告)号：US08552773B2
公开(公告)日：2013-10-08
申请号：US13510578
申请日：2010-09-17
申请人： Neil Edwin Thomas
发明人： Neil Edwin Thomas
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/10 , H03L7/185 , H03L7/189 , H03L2207/06 , H03L2207/12
摘要： A phase locked loop (10) comprising: a tuneable oscillator (12); a mixer-based phase sensitive detector (18) to receive input signals from the tuneable oscillator (12) and a reference signal (20); a cycle slip detector (26) to receive input signals from the tuneable oscillator (12) and the reference signal (20), the cycle slip detector (26) being configured to generate an output signal when two consecutive pulses are present in one of its input signals without an intervening pulse in the other of its input signals; coarse tune signal means (32, 34) to receive the output signal generated by the cycle slip detector; and adding means (24) for adding a signal output by the coarse signal means (32, 34) to a signal output by the phase sensitive detector (18) to control the frequency of the tuneable oscillator (12).
摘要翻译：一种锁相环（10），包括：可调谐振荡器（12）; 基于混频器的相位敏感检测器（18），用于接收来自可调谐振荡器（12）的输入信号和参考信号（20）; 循环滑移检测器（26），用于接收来自可调谐振荡器（12）和参考信号（20）的输入信号，周期滑移检测器（26）被配置为当两个连续脉冲存在于其中的一个中时产生输出信号在其输入信号中没有中间脉冲的输入信号; 粗调信号装置（32,34），用于接收由循环滑移检测器产生的输出信号; 和加法装置（24），用于将由粗信号装置输出的信号（32,34）加到由相敏检测器（18）输出的信号上，以控制可调谐振荡器（12）的频率。

7. 发明授权

US08466724B2 Frequency synthesizer 失效
标题翻译：频率合成器
公开(公告)号：US08466724B2
公开(公告)日：2013-06-18
申请号：US12736023
申请日：2009-03-02
申请人： Tsukasa Kobata
发明人： Tsukasa Kobata
IPC分类号： H03L7/06
CPC分类号： H03L7/189 , H03L7/085 , H03L7/087 , H03L7/093 , H03L7/10
摘要： Provided is a frequency synthesizer capable of fine setting over a wide band and having a wide frequency pull-in range. A sine wave signal of an output frequency of a voltage controlled oscillating part is quadrature-detected, and in a PLL utilizing a vector rotating at a frequency (velocity) equal to a difference from a frequency of a frequency signal used for the detection, a frequency pull-in means integrates a first constant for increasing the output frequency as a pull-in voltage when a control voltage from the PLL to the voltage controlled oscillating part is larger than a prescribed set range, and integrates a second constant for decreasing the output frequency as the pull-in voltage when the control voltage is smaller than the set range. Then, an adding means adds the control voltage from the PLL and the pull-in voltage from the frequency pull-in means to output an addition result to the voltage controlled oscillating part.
摘要翻译：提供了能够在宽频带上精细设置并具有宽频率拉入范围的频率合成器。电压控制振荡部分的输出频率的正弦波信号被正交检测，并且在利用以与用于检测的频率信号的频率的差等于频率（速度））旋转的矢量的PLL中，当从PLL到受压振荡部分的控制电压大于规定的设定范围时，频率引入装置将用于增加输出频率的第一常数作为拉入电压进行积分，并且积分用于减小输出的第二常数频率作为控制电压小于设定范围时的拉入电压。然后，加法装置将来自PLL的控制电压和来自频率引入装置的引入电压相加，以将相加结果输出到受电压控制的振荡部分。

8. 发明授权

US07821344B2 VCO driving circuit and frequency synthesizer 有权
标题翻译： VCO驱动电路和频率合成器
公开(公告)号：US07821344B2
公开(公告)日：2010-10-26
申请号：US12219452
申请日：2008-07-22
申请人： Yasuo Kitayama , Hiroki Kimura , Naoki Onishi , Nobuo Tsukamoto
发明人： Yasuo Kitayama , Hiroki Kimura , Naoki Onishi , Nobuo Tsukamoto
IPC分类号： H03L7/085 , H03L1/02
CPC分类号： H03L7/093 , H03L1/026 , H03L7/107 , H03L7/1075 , H03L7/18 , H03L7/189
摘要： A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.
摘要翻译： VCO驱动电路和频率合成器，其中从VCO控制端子观察的阻抗减小，以防止VCO相位噪声特性降级。 VCO驱动电路和具有VCO驱动电路的频率合成器，其包括具有粗略调整频率的接收数字数据的粗调DAC以输出模拟信号; 微调DAC，其接收具有微调频率的数字数据，以输出模拟信号; 低响应速度LPF5，其从粗调DAC输出信号中去除噪声，然后将所得到的信号作为输入提供给VCO控制端; 高响应速度LPF7，其将来自微调DAC的输出信号转换为电压，从而平滑信号; 将LPF5的输入级与LPF7的输入级连接的电阻; 以及用于提供电容耦合的电容器，使得LPF7的输出被添加到LPF5的输出。

9. 发明申请

US20090039967A1 PHASED-LOCKED LOOP (PLL) SYNTHESIZER-SYNTHESIZER WITH IMPROVED VOLTAGE-CONTROLLED OSCILLATOR (VCO) PRE-TUNING 有权
标题翻译：具有改进的电压控制振荡器（VCO）预调节的锁相环（PLL）合成器合成器
公开(公告)号：US20090039967A1
公开(公告)日：2009-02-12
申请号：US11816076
申请日：2006-02-02
申请人： Alois Schechinger
发明人： Alois Schechinger
IPC分类号： H03L7/00
CPC分类号： H03L7/107 , H03L7/099 , H03L7/189 , H03L2207/06
摘要： An apparatus for providing Phased-Locked Loop (PLL) synthesis comprises a phase detector, at least one switchable filter, an oscillator controlled by a control voltage (uPLL) and a divider. The controlled oscillator has two inputs, wherein the control voltage (uPLL) is coupled to a first input, and a selection voltage (uSET) for rough frequency adjustment is coupled to a second input. Both voltages establish the frequency of the oscillator.
摘要翻译：用于提供相位锁定环路（PLL）合成的装置包括相位检测器，至少一个可切换滤波器，由控制电压（uPLL）和分频器控制的振荡器。受控振荡器具有两个输入，其中控制电压（uPLL）耦合到第一输入，并且用于粗频率调整的选择电压（uSET）耦合到第二输入。两个电压都建立振荡器的频率。

10. 发明授权

US07148754B2 Self-tunable phase lock loop 有权
标题翻译：自适应锁相环
公开(公告)号：US07148754B2
公开(公告)日：2006-12-12
申请号：US11026562
申请日：2004-12-30
申请人： Gerhard Kaminski
发明人： Gerhard Kaminski
IPC分类号： H03L7/06
CPC分类号： H03L7/189
摘要： The present invention provides a method and an apparatus for selectively pretuning and updating a phase lock loop, deployed in an integrated circuit including an agile radio, such as a wideband or an ultra wideband frequency agile radio in a telecommunication system, for example, a reconfigurable multiband and/or multistandard mobile communication system. In one embodiment, a phase lock loop may comprise a digital storage having a first desired frequency. An oscillator may provide an oscillator frequency and a frequency generator circuit capable of producing at least one control signal may cause the oscillator to adapt the oscillator frequency based on the first desired frequency in response to a trigger signal. A pretune unit may apply a pretune voltage to a tuning element to cause the oscillator to calibrate the oscillator frequency to the first desired frequency. An output voltage may be added at the output of a loop filter to the pretune voltage to tune the output voltage of the loop filter such that to set the oscillator frequency substantially at the first desired frequency. An update unit may automatically determine whether one or more parameters of a phase lock loop unit have changed to dynamically update the pretune voltage.
摘要翻译：本发明提供了一种用于选择性地预处理和更新锁相环的方法和装置，其部署在包括敏捷无线电的集成电路中，所述集成电路例如是电信系统中的宽带或超宽带频率捷变无线电，例如可重新配置多频段和/或多标准移动通信系统。在一个实施例中，锁相环可以包括具有第一期望频率的数字存储器。振荡器可以提供振荡器频率，并且能够产生至少一个控制信号的频率发生器电路可以响应于触发信号而使振荡器基于第一期望频率来适应振荡器频率。预约单元可以向调谐元件施加预调电压，以使振荡器将振荡器频率校准到第一期望频率。可以在环路滤波器的输出处将输出电压加到预调电压上，以调谐环路滤波器的输出电压，使得将振荡器频率基本上设置在第一所需频率。更新单元可以自动确定锁相环单元的一个或多个参数是否已经改变以动态地更新预制电压。

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