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    • 1. 发明申请
    • SINGLE-WIRE INTERFACE BUS TRANSCIVER SYSTEM BASED ON I2C-BUS, AND ASSOCIATED METHOD FOR COMMUNICATION OF SINGLE-WIRE INTERFACE BUS
    • 基于I2C总线的单线接口总线交换机系统,以及单线接口总线通信的相关方法
    • US20170024354A1
    • 2017-01-26
    • US15301871
    • 2015-04-09
    • NXP B.V.
    • Hongyun ZhangJian QingZhongmeng Chen
    • G06F13/42G06F13/40G06F13/364
    • G06F13/4291G06F13/364G06F13/387G06F13/404G06F13/4295
    • There is disclosed a single-wire Interface bus transceiver system comprising: an I2C master, a master transceiver, a signal wire, a slave transceiver and an I2C slave, wherein the master transceiver is adapted to encode master data SDA and master clock SCL received from I2C master using Manchester code, generate master single wire signal and transfer it to the slave transceiver through the signal wire, the master transceiver is also adapted to decode Manchester-encoded slave signal received from the signal wire and transfer the decoded slave data to I2C master; the slave transceiver is adapted to encode slave data received from I2C slave using Manchester code, generate slave single wire signal and transfer it to the master transceiver through the signal wire, the slave transceiver is also adapted to decode Manchester-encoded master signal received from the signal wire, generate the recovered master clock and transfer the decoded master data and recovered master clock to I2C slave.
    • 公开了一种单线接口总线收发器系统,包括:I2C主机,主收发器,信号线,从机收发器和I2C从机,其中主收发器适于编码主数据SDA和主时钟SCL从 I2C主机使用曼彻斯特码,生成主单线信号并通过信号线将其传输到从机收发器,主收发器还适用于解码从信号线接收的曼彻斯特编码的从机信号,并将解码的从属数据传输到I2C主机 ; 从机收发器适用于使用曼彻斯特码编码从I2C从机接收的从机数据,产生从机单线信号,并通过信号线将其传送到主收发器,从机收发器还适用于解码从主机收到的曼彻斯特编码的主信号 信号线,产生恢复的主时钟,并将解码的主数据和恢复的主时钟传送到I2C从机。
    • 8. 发明申请
    • SWITCHED CAPACITOR CONVERTER
    • US20220385179A1
    • 2022-12-01
    • US17443972
    • 2021-07-29
    • NXP B.V.
    • Dongyong ZhuBo CaiXinDong DuanFeng CongJian Qing
    • H02M3/07H03K17/16H03K17/0812H02M1/08H02M3/158
    • The disclosure relates to a switched capacitor converter with gate driving circuits for limiting currents provided by switching field effect transistors. Embodiments disclosed include a switched capacitor converter (100), SCC, comprising a plurality of gate driver circuits (101a-d, 200, 300) arranged to provide a gate voltage signal to a respective power FET (102a-d) in response to a respective input switching signal (sw1_in, sw2_in, sw3_in, sw4_in, IN), wherein each gate driver circuit (101a-d, 200, 300) comprises a first gate driver module (206) and a second gate driver module (207), the gate driver circuit (101a-d, 200, 300) configured to operate in: a first mode in which the first gate driver module (206) provides the gate voltage signal to a respective power FET (102a-d, 205) in response to an input switching signal (IN) at an input (203) of the first gate driver module (206) causing the gate voltage signal to switch between first and second voltage rails (201, 202) by operation of first and second switches (208, 209) connected between the pair of voltage rails (201, 202); and a second mode in which, in response to enabling of a current limit switching signal (climit_en), the first gate driver module disables switching of one of the first and second switches (208, 209) and the second gate driver module (207) operates to limit a current provided to the respective power FET (102a-d, 205).