专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07893550B2 Semiconductor package comprising alignment members 有权
标题翻译：半导体封装包括对准构件
公开(公告)号：US07893550B2
公开(公告)日：2011-02-22
申请号：US12750915
申请日：2010-03-31
申请人： Na-rae Shin , Dong-han Kim
发明人： Na-rae Shin , Dong-han Kim
IPC分类号： H01L23/544
CPC分类号： H01L23/4985 , H01L23/544 , H01L24/50 , H01L24/86 , H01L2223/5442 , H01L2223/54426 , H01L2223/5448 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014
摘要： A semiconductor package comprising alignment members is provided. The semiconductor package includes a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate including a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further includes a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member.
摘要翻译：提供了包括对准构件的半导体封装。半导体封装包括半导体管芯，设置在半导体管芯的第一表面上的第一连接端子和包括基板部分的带基板，以及设置在基板部分上并对应于第一连接端子设置的第二连接端子。半导体封装还包括设置在半导体管芯的第一表面上的第一对准部件和设置在带基板的基板部分上并对应于第一对准部件设置的第二对准部件。

2. 发明授权

US07257096B2 Global system for mobile communication (GSM) and general packet radio service (GPRS) power ramping controller and associated power ramping method 失效
标题翻译：全球移动通信系统（GSM）和通用分组无线业务（GPRS）功率斜坡控制器及相关功率斜坡法
公开(公告)号：US07257096B2
公开(公告)日：2007-08-14
申请号：US10886925
申请日：2004-07-08
申请人： Dong-han Kim
发明人： Dong-han Kim
IPC分类号： H04B7/185
CPC分类号： H04W52/36 , H03G3/3047 , H04B1/0475 , H04B2001/0416 , H04W52/52
摘要： A (GSM) and (GPRS) power ramping controller and an associated power ramping method are provided. Each frame to be transmitted has a plurality of slots, and each slot has a data period and a guard period for classifying continuous slots of the plurality of slots, and the guard period has a U-shaped power level waveform. The power ramping controller includes a ramp memory for dividing power levels of the of the plurality of slots within a power level range and storing the divided power level range from a lowermost address to an uppermost address; a counter for allocating a start address of the ramp memory for designating a power level of a first slot of the plurality of slots to a lower index and a final address of the ramp memory for designating a power level of a second slot of the plurality of slots to an upper index; and a controller for dividing the guard period into a number of indices of the counter, increasing the lower index of the counter by 1 and subtracting 1 from the start address, decreasing the upper index of the counter by 1 and subtracting 1 from the final address, designating an address, at a time when a difference obtained by subtracting the start address from the final address is 0 or 1, as an inflection address, and determining ramp steps as power levels stored in addresses corresponding to the number of indices of the counter at the guard period.
摘要翻译：提供了（GSM）和（GPRS）功率斜坡控制器以及相关的功率斜坡方法。要发送的每个帧具有多个时隙，并且每个时隙具有用于对多个时隙中的连续时隙进行分类的数据周期和保护周期，并且保护周期具有U形功率电平波形。功率斜坡控制器包括斜坡存储器，用于将多个时隙中的功率电平分配在功率电平范围内，并将分频功率电平范围从最低地址存储到最高地址; 用于将用于指定多个时隙中的第一时隙的功率电平指定到较低索引的斜坡存储器的起始地址和斜坡存储器的最终地址的计数器，用于指定多个时隙中的第二时隙的功率电平插槽到上索引; 以及控制器，用于将保护周期分成多个计数器的索引，将计数器的下索引增加1并从起始地址减1，将计数器的上索引减1，并从最终地址减1 在通过从最终地址减去开始地址而获得的差值为0或1作为拐点地址时，指定地址，并且将斜坡步长确定为存储在与计数器的索引数相对应的地址中的功率电平在守卫期间。

3. 发明申请

US20100121910A1 Method and System for Transmitting Data Using Traffic Distribution for Each Line Between Server and Client Connected by Virtual Interface 有权
标题翻译：通过虚拟接口连接的服务器和客户端之间的每一行的流量分配传输数据的方法和系统
公开(公告)号：US20100121910A1
公开(公告)日：2010-05-13
申请号：US12527414
申请日：2008-08-19
申请人： Dong-han Kim
发明人： Dong-han Kim
IPC分类号： G06F15/16
CPC分类号： H04L47/10 , H04L45/00 , H04L45/245 , H04L47/125
摘要： The present invention discloses a method comprising a first step of the client transmitting a bandwidth test request signal to the server; a second step of the server transmitting a test request approval signal to the client; a third step of the client conducting a bandwidth test for respective lines; a fourth step of the client transmitting results of the bandwidth test to the server; fifth step of the server setting first traffic distribution weights; a sixth step of the client setting second traffic distribution weights; a seventh step of the server distributing data to respective lines depending on the first traffic distribution weights and transmitting the distributed data to the client and the client distributing data to respective lines depending on the second traffic distribution weights and transmitting the distributed data to the server.
摘要翻译：本发明公开了一种方法，包括客户端向服务器发送带宽测试请求信号的第一步骤; 服务器向客户端发送测试请求许可信号的第二步骤; 客户端针对各行进行带宽测试的第三步; 客户端向服务器发送带宽测试结果的第四步骤; 服务器设置第一个流量分配权重的第五步; 客户端设置第二个流量分配权重的第六步; 所述服务器根据所述第一流量分配权重将数据分发到各个线路并将所述分布式数据发送给所述客户机，并且所述客户端根据所述第二业务分配权重将数据分发到各个线路，并将所述分布式数据发送到所述服务器的第七步骤。

4. 发明申请

US20100001392A1 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US20100001392A1
公开(公告)日：2010-01-07
申请号：US12458231
申请日：2009-07-06
申请人： Young-sang Cho , Dong-han Kim , Dae-woo Son , Ye-chung Chung
发明人： Young-sang Cho , Dong-han Kim , Dae-woo Son , Ye-chung Chung
IPC分类号： H01L23/544 , H01L23/488
CPC分类号： H01L23/544 , H01L23/498 , H01L24/81 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2223/5448 , H01L2224/81121 , H01L2224/81801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082
摘要： Provided is a semiconductor package including a substrate and a semiconductor chip formed on the substrate. The semiconductor chip may include a chip alignment mark on a surface of the semiconductor chip, and wiring patterns formed on a surface of the substrate, wherein the chip alignment mark is bonded to the wiring patterns. Accordingly, the surface area of the semiconductor chip may be reduced.
摘要翻译：提供了一种半导体封装，其包括形成在基板上的基板和半导体芯片。半导体芯片可以包括在半导体芯片的表面上的芯片对准标记，以及形成在基板的表面上的布线图案，其中芯片对准标记被接合到布线图案。因此，可以减小半导体芯片的表面积。

5. 发明申请

US20070138654A1 Semiconductor chip, film substrate, and related semiconductor chip package 有权
标题翻译：半导体芯片，薄膜基板及相关半导体芯片封装
公开(公告)号：US20070138654A1
公开(公告)日：2007-06-21
申请号：US11589138
申请日：2006-10-30
申请人： Dong-han Kim
发明人： Dong-han Kim
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , G02F1/13452 , H01L23/4985 , H01L23/50 , H01L24/06 , H01L24/16 , H01L2224/0401 , H01L2224/06155 , H01L2224/16225 , H01L2924/01079 , H01L2924/14 , H01L2924/15173 , H01L2924/18161 , H05K3/323 , H05K2201/10136 , H05K2201/10446
摘要： A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip.
摘要翻译：提供一种半导体芯片封装，其包括装载在半导体芯片上的薄膜基板和半导体芯片。半导体芯片包括多个输入焊盘和多个输出焊盘。输入焊盘的电源输入焊盘形成在与形成其它输入焊盘的半导体芯片的边缘不同的边缘处。薄膜基板包括输入线和输出线。薄膜基板的输入线连接到半导体芯片的相应的输入焊盘，其输出线连接到半导体芯片的对应的输出焊盘。

6. 发明授权

US08648477B2 Semiconductor chip, film substrate, and related semiconductor chip package 有权
标题翻译：半导体芯片，薄膜基板及相关半导体芯片封装
公开(公告)号：US08648477B2
公开(公告)日：2014-02-11
申请号：US12836321
申请日：2010-07-14
申请人： Dong-han Kim
发明人： Dong-han Kim
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , G02F1/13452 , H01L23/4985 , H01L23/50 , H01L24/06 , H01L24/16 , H01L2224/0401 , H01L2224/06155 , H01L2224/16225 , H01L2924/01079 , H01L2924/14 , H01L2924/15173 , H01L2924/18161 , H05K3/323 , H05K2201/10136 , H05K2201/10446
摘要： A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip.
摘要翻译：提供一种半导体芯片封装，其包括装载在半导体芯片上的薄膜基板和半导体芯片。半导体芯片包括多个输入焊盘和多个输出焊盘。输入焊盘的电源输入焊盘形成在与形成其它输入焊盘的半导体芯片的边缘不同的边缘处。薄膜基板包括输入线和输出线。薄膜基板的输入线连接到半导体芯片的相应的输入焊盘，其输出线连接到半导体芯片的对应的输出焊盘。

7. 发明授权

US08647976B2 Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same 有权
标题翻译：具有在顶部和底部衬底表面上的测试焊盘的半导体封装及其测试方法
公开(公告)号：US08647976B2
公开(公告)日：2014-02-11
申请号：US13348767
申请日：2012-01-12
申请人： Eun-seok Song , Dong-han Kim , Hee-seok Lee
发明人： Eun-seok Song , Dong-han Kim , Hee-seok Lee
IPC分类号： H01L21/4763
CPC分类号： G01R31/2884 , H01L22/32 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.
摘要翻译：公开了半导体封装和测试方法。封装包括具有顶表面和底表面的衬底，安装在衬底的位于中心的半导体芯片安装区域中的半导体芯片以及设置在衬底的顶表面和底表面上的多个测试焊盘，并且包括第一组测试焊盘配置在衬底的顶表面和底表面上并且具有在衬底的相应顶部和底部表面上方的第一高度，以及设置在衬底的下表面上并具有大于第一衬底的第二高度的第二组测试焊盘其中第二组测试垫中的每一个包括附接到其上的焊球。

8. 发明申请

US20120068349A1 TAPE PACKAGE 有权
标题翻译：胶带包装
公开(公告)号：US20120068349A1
公开(公告)日：2012-03-22
申请号：US13223624
申请日：2011-09-01
申请人： Dong-han Kim , So-young Lim
发明人： Dong-han Kim , So-young Lim
IPC分类号： H01L23/52
CPC分类号： H01L23/4985 , H01L23/49838 , H01L24/06 , H01L2224/0603 , H01L2224/06155 , H01L2924/09701 , H01L2924/12041 , H01L2924/12044 , H01L2924/1436 , H01L2924/1437 , H01L2924/351 , H01L2924/00
摘要： A tape package providing a plurality of input and output portions each having a minimum pitch. The tape package includes a tape wiring substrate including first and second wirings, and a semiconductor chip mounted on the tape wiring substrate, and including a first edge, a first pad disposed adjacent to the first edge, and a second pad disposed to be farther spaced apart from the first edge than the first pad, where the first wiring is connected to a portion of the first pad that is spaced from the first edge by a first distance, and where the second wiring is connected to a portion of the second pad that is spaced from the first edge by a second distance that is greater than the first distance.
摘要翻译：一种提供多个具有最小间距的输入和输出部分的磁带封装。所述带包装包括包括第一和第二布线的带布线基板，以及安装在所述带布线基板上的半导体芯片，并且包括第一边缘，邻近所述第一边缘设置的第一焊盘和设置成更远的间隔的第二焊盘除了第一边缘之外，第一布线连接到第一焊盘的与第一边缘间隔开第一距离的部分，并且其中第二布线连接到第二焊盘的一部分，与第一边缘间隔开大于第一距离的第二距离。

9. 发明授权

US07763986B2 Semiconductor chip, film substrate, and related semiconductor chip package 有权
标题翻译：半导体芯片，薄膜基板及相关半导体芯片封装
公开(公告)号：US07763986B2
公开(公告)日：2010-07-27
申请号：US11589138
申请日：2006-10-30
申请人： Dong-han Kim
发明人： Dong-han Kim
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , G02F1/13452 , H01L23/4985 , H01L23/50 , H01L24/06 , H01L24/16 , H01L2224/0401 , H01L2224/06155 , H01L2224/16225 , H01L2924/01079 , H01L2924/14 , H01L2924/15173 , H01L2924/18161 , H05K3/323 , H05K2201/10136 , H05K2201/10446
摘要： A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip.
摘要翻译：提供一种半导体芯片封装，其包括装载在半导体芯片上的薄膜基板和半导体芯片。半导体芯片包括多个输入焊盘和多个输出焊盘。输入焊盘的电源输入焊盘形成在与形成其它输入焊盘的半导体芯片的边缘不同的边缘处。薄膜基板包括输入线和输出线。薄膜基板的输入线连接到半导体芯片的相应的输入焊盘，其输出线连接到半导体芯片的对应的输出焊盘。

10. 发明授权

US09129972B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US09129972B2
公开(公告)日：2015-09-08
申请号：US12458231
申请日：2009-07-06
申请人： Young-sang Cho , Dong-han Kim , Dae-woo Son , Ye-chung Chung
发明人： Young-sang Cho , Dong-han Kim , Dae-woo Son , Ye-chung Chung
IPC分类号： H01L23/544 , H01L23/48 , H01L23/498 , H01L23/00
CPC分类号： H01L23/544 , H01L23/498 , H01L24/81 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2223/5448 , H01L2224/81121 , H01L2224/81801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082
摘要： Provided is a semiconductor package including a substrate and a semiconductor chip formed on the substrate. The semiconductor chip may include a chip alignment mark on a surface of the semiconductor chip, and wiring patterns formed on a surface of the substrate, wherein the chip alignment mark is bonded to the wiring patterns. Accordingly, the surface area of the semiconductor chip may be reduced.
摘要翻译：提供了一种半导体封装，其包括形成在基板上的基板和半导体芯片。半导体芯片可以包括在半导体芯片的表面上的芯片对准标记，以及形成在基板的表面上的布线图案，其中芯片对准标记被接合到布线图案。因此，可以减小半导体芯片的表面积。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式