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1. 发明授权

US09082817B2 Growth of multi-layer group III-nitride buffers on large-area silicon substrates and other substrates 有权
公开(公告)号：US09082817B2
公开(公告)日：2015-07-14
申请号：US14060128
申请日：2013-10-22
申请人： National Semiconductor Corporation
发明人： Sandeep R. Bahl , Jamal Ramdani
IPC分类号： H01L21/86 , H01L21/762 , H01L21/02 , H01L29/10 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/205 , H01L21/76 , H01L29/06 , H01L23/485 , H01L27/06 , H01L27/088
CPC分类号： H01L21/762 , H01L21/0237 , H01L21/02381 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L21/02639 , H01L21/7605 , H01L23/485 , H01L27/0605 , H01L27/088 , H01L29/0649 , H01L29/1075 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7787 , H01L2924/0002 , H01L2924/00
摘要： A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.

2. 发明申请

US20140312358A1 NORMALLY-OFF GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICES 审中-公开
标题翻译：基于氮化镓的半导体器件
公开(公告)号：US20140312358A1
公开(公告)日：2014-10-23
申请号：US14319490
申请日：2014-06-30
申请人： National Semiconductor Corporation
发明人： Jamal Ramdani
IPC分类号： H01L29/225 , H01L29/778
CPC分类号： H01L29/225 , H01L29/2003 , H01L29/66462 , H01L29/7786
摘要： A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride.
摘要翻译：一种方法包括在半导体器件中形成松弛层。该方法还包括在松弛层上形成拉伸层，其中拉伸层具有拉伸应力。该方法还包括在松弛层上形成压缩层，其中压缩层具有压应力。压缩层具有大致等于或大于松弛，拉伸和压缩层中的自发极化的压电极化。压缩层中的压电极化可能与压缩层中的自发极化方向相反。松弛层可以包括氮化镓，拉伸层可以包括氮化镓铝，并且压缩层可以包括铝铟镓氮。

3. 发明申请

US20140094005A1 Enhancement-Mode GaN MOSFET with Low Leakage Current and Improved Reliability 审中-公开
标题翻译：具有低漏电流的增强型GaN MOSFET和改进的可靠性
公开(公告)号：US20140094005A1
公开(公告)日：2014-04-03
申请号：US14091606
申请日：2013-11-27
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： Jamal Ramdani
IPC分类号： H01L29/66 , H01L21/02
CPC分类号： H01L29/66431 , H01L21/02458 , H01L21/0254 , H01L21/28264 , H01L29/1054 , H01L29/2003 , H01L29/205 , H01L29/513 , H01L29/518 , H01L29/66462 , H01L29/66522 , H01L29/7787
摘要： An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO2/Si3N4 gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si3N4 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO2 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the leakage current.
摘要翻译：通过在AlGaN（或InAlGaN）阻挡层上利用SiO 2 / Si 3 N 4栅极绝缘层，形成具有低漏电流和提高的可靠性的增强型GaN MOSFET。 SiO 2 / Si 3 N 4栅极绝缘层的Si 3 N 4部分显着地减少了在栅极绝缘层和阻挡层之间的接合处的界面态的形成，而SiO 2 / Si 3 N 4栅极绝缘层的SiO 2部分显着降低了漏电流。

4. 发明授权

US09111753B2 Backside stress compensation method for making gallium nitride or other nitride-based semiconductor devices 有权
标题翻译：制造氮化镓或其他氮化物类半导体器件的背面应力补偿方法
公开(公告)号：US09111753B2
公开(公告)日：2015-08-18
申请号：US14301916
申请日：2014-06-11
申请人： National Semiconductor Corporation
发明人： Jamal Ramdani
IPC分类号： H01L21/20 , H01L21/36 , H01L21/02 , H01L29/778 , H01L29/20
CPC分类号： H01L21/02667 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02592 , H01L21/02595 , H01L21/02658 , H01L29/2003 , H01L29/7787
摘要： A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process. The amorphous or microcrystalline material could create no or a smaller amount of stress on the substrate, and the crystallized material could create a larger amount of stress on the substrate.
摘要翻译：一种方法包括在半导体衬底的第一侧上形成应力补偿层，并在衬底的第二面上形成III族氮化物层。通过III族氮化物层在衬底上产生的应力通过应力补偿层在衬底上产生的应力至少部分地减小。形成应力补偿层可以包括从非晶或微晶材料形成应力补偿层。此外，该方法可以包括在随后在衬底的第二侧上形成一层或多层之后使无定形或微晶材料结晶。在随后形成III族氮化物层和/或退火过程期间，可能发生非晶或微晶材料的结晶。无定形或微晶材料在基底上不会产生或少量的应力，并且结晶的材料可能在基底上产生更大量的应力。

5. 发明授权

US09385199B2 Normally-off gallium nitride-based semiconductor devices 有权
标题翻译：通常的氮化镓基半导体器件
公开(公告)号：US09385199B2
公开(公告)日：2016-07-05
申请号：US14319490
申请日：2014-06-30
申请人： National Semiconductor Corporation
发明人： Jamal Ramdani
IPC分类号： H01L31/0336 , H01L29/225 , H01L29/66 , H01L29/778 , H01L29/20
CPC分类号： H01L29/225 , H01L29/2003 , H01L29/66462 , H01L29/7786
摘要： A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride.
摘要翻译：一种方法包括在半导体器件中形成松弛层。该方法还包括在松弛层上形成拉伸层，其中拉伸层具有拉伸应力。该方法还包括在松弛层上形成压缩层，其中压缩层具有压应力。压缩层具有大致等于或大于松弛，拉伸和压缩层中的自发极化的压电极化。压缩层中的压电极化可能与压缩层中的自发极化方向相反。松弛层可以包括氮化镓，拉伸层可以包括氮化镓铝，并且压缩层可以包括铝铟镓氮。

6. 发明授权

US09064928B2 Growth of multi-layer group III-nitride buffers on large-area silicon substrates and other substrates 有权
标题翻译：在大面积硅衬底和其他衬底上生长多层III族氮化物缓冲液
公开(公告)号：US09064928B2
公开(公告)日：2015-06-23
申请号：US14059613
申请日：2013-10-22
申请人： National Semiconductor Corporation
发明人： Sandeep R. Bahl , Jamal Ramdani
IPC分类号： H01L21/02 , H01L21/762 , H01L29/10 , H01L29/66 , H01L29/778 , H01L29/20 , H01L29/205 , H01L21/76 , H01L29/06 , H01L23/485 , H01L27/06 , H01L27/088
CPC分类号： H01L21/762 , H01L21/0237 , H01L21/02381 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L21/02639 , H01L21/7605 , H01L23/485 , H01L27/0605 , H01L27/088 , H01L29/0649 , H01L29/1075 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7787 , H01L2924/0002 , H01L2924/00
摘要： A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.
摘要翻译：一种方法包括在半导体衬底上形成第一外延层并蚀刻第一外延层以形成多个分离的第一外延区域。该方法还包括在蚀刻的第一外延层上形成第二外延层。每个外延层包括至少一个III族氮化物，并且外延层共同形成缓冲器。该方法还包括在缓冲器上形成器件层，并使用该器件层制造半导体器件。第二外延层可以包括基本上仅在第一外延区上的第二外延区。第二外延层还可以覆盖第一外延区域和衬底，并且第二外延层可以被蚀刻也可以不被蚀刻。可以在用于形成第二外延层的相同操作期间形成器件层。

7. 发明授权

US08940593B2 Enhancement-mode GaN MOSFET with low leakage current and improved reliability 有权
标题翻译：增强型GaN MOSFET具有低漏电流和可靠性
公开(公告)号：US08940593B2
公开(公告)日：2015-01-27
申请号：US14091606
申请日：2013-11-27
申请人： National Semiconductor Corporation
发明人： Jamal Ramdani
IPC分类号： H01L21/338 , H01L21/336 , H01L29/66 , H01L21/28 , H01L29/10 , H01L29/51 , H01L29/778 , H01L21/02 , H01L29/20 , H01L29/205
CPC分类号： H01L29/66431 , H01L21/02458 , H01L21/0254 , H01L21/28264 , H01L29/1054 , H01L29/2003 , H01L29/205 , H01L29/513 , H01L29/518 , H01L29/66462 , H01L29/66522 , H01L29/7787
摘要： An enhancement-mode GaN MOSFET with a low leakage current and an improved reliability is formed by utilizing a SiO2/Si3N4 gate insulation layer on an AlGaN (or InAlGaN) barrier layer. The Si3N4 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the formation of interface states at the junction between the gate insulation layer and the barrier layer, while the SiO2 portion of the SiO2/Si3N4 gate insulation layer significantly reduces the leakage current.
摘要翻译：通过在AlGaN（或InAlGaN）阻挡层上利用SiO 2 / Si 3 N 4栅极绝缘层，形成具有低漏电流和提高的可靠性的增强型GaN MOSFET。 SiO 2 / Si 3 N 4栅极绝缘层的Si 3 N 4部分显着地减少了在栅极绝缘层和阻挡层之间的接合处的界面态的形成，而SiO 2 / Si 3 N 4栅极绝缘层的SiO 2部分显着降低了漏电流。

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