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1. 发明授权

US07633316B2 Transmission gate multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US07633316B2
公开(公告)日：2009-12-15
申请号：US12256582
申请日：2008-10-23
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

2. 发明申请

US20090096486A1 Structure for Transmission Gate Multiplexer 审中-公开
标题翻译：传输门复用器的结构
公开(公告)号：US20090096486A1
公开(公告)日：2009-04-16
申请号：US12028940
申请日：2008-02-11
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/005
摘要： A technique and design structure for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术和设计结构包括从多个传输门组中选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

3. 发明授权

US07466165B1 Transmission gate multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US07466165B1
公开(公告)日：2008-12-16
申请号：US11854604
申请日：2007-09-13
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

4. 发明申请

US20090072863A1 Transmission Gate Multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US20090072863A1
公开(公告)日：2009-03-19
申请号：US12256582
申请日：2008-10-23
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20 , G06F9/305
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

5. 发明申请

US20080303553A1 METHOD AND APPARATUS FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER 有权
标题翻译：一种可配置低功率高风扇多路复用器的方法和装置
公开(公告)号：US20080303553A1
公开(公告)日：2008-12-11
申请号：US11759426
申请日：2007-06-07
申请人： OWEN CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： OWEN CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K19/0008 , H03K17/005
摘要： A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高风扇多路复用器（MUX）。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使得相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

6. 发明授权

US07693701B2 Structure for a configurable low power high fan-in multiplexer 失效
标题翻译：可配置低功耗高风扇多路复用器的结构
公开(公告)号：US07693701B2
公开(公告)日：2010-04-06
申请号：US12132501
申请日：2008-06-03
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： G06F17/50 , H03K19/094
CPC分类号： H03K17/005 , H03K19/0008
摘要： A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高扇入多路复用器（MUX）及其设计结构。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

7. 发明授权

US07466164B1 Method and apparatus for a configurable low power high fan-in multiplexer 有权
标题翻译：用于可配置低功率高风扇多路复用器的方法和装置
公开(公告)号：US07466164B1
公开(公告)日：2008-12-16
申请号：US11759426
申请日：2007-06-07
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： H03K19/94
CPC分类号： H03K19/0008 , H03K17/005
摘要： A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高风扇多路复用器（MUX）。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

8. 发明申请

US20080303554A1 STRUCTURE FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER 失效
标题翻译：可配置低功率高风扇多路复用器的结构
公开(公告)号：US20080303554A1
公开(公告)日：2008-12-11
申请号：US12132501
申请日：2008-06-03
申请人： Owen CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/005 , H03K19/0008
摘要： A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高扇入多路复用器（MUX）及其设计结构。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

9. 发明授权

US08354858B2 Apparatus and method for hardening latches in SOI CMOS devices 有权
标题翻译：用于硬化SOI CMOS器件中的锁存器的装置和方法
公开(公告)号：US08354858B2
公开(公告)日：2013-01-15
申请号：US12987106
申请日：2011-01-08
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

10. 发明授权

US07888959B2 Apparatus and method for hardening latches in SOI CMOS devices 有权
标题翻译：用于硬化SOI CMOS器件中的锁存器的装置和方法
公开(公告)号：US07888959B2
公开(公告)日：2011-02-15
申请号：US11857596
申请日：2007-09-19
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

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