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1. 发明授权

US07190191B1 Over-voltage tolerant input buffer having hot-plug capability 有权
标题翻译：具有热插拔功能的过压容忍输入缓冲器
公开(公告)号：US07190191B1
公开(公告)日：2007-03-13
申请号：US10786204
申请日：2004-02-24
申请人： Manish Kumar Mathur , Gajender Rohilla
发明人： Manish Kumar Mathur , Gajender Rohilla
IPC分类号： H03K19/94 , G06F13/00
CPC分类号： H02H9/004 , H03K19/00315
摘要： An input buffer circuit and associated method operable in a normal mode and a hot-plug mode. In one example, the input buffer has an input and a buffer output, and the input buffer may include a pull-up path coupled between a first circuit supply and the buffer output; a pull-down path coupled between the buffer output and a ground reference voltage; a first transistor coupled between the input and the pull-up path to activate the pull-up path; a second transistor coupled between the input and the pull-down path to activate the pull-down path; and a third transistor for protecting the pull-up path from over-voltage. The input buffer circuit may be configured to prevent an over-voltage condition on each of the plurality of transistors and the input buffer circuit may be configured to allow a hot-plug operation.
摘要翻译：一种输入缓冲电路和相关联的方法，可在正常模式和热插拔模式下工作。在一个示例中，输入缓冲器具有输入和缓冲器输出，并且输入缓冲器可以包括耦合在第一电路电源和缓冲器输出之间的上拉通路; 耦合在缓冲器输出和接地参考电压之间的下拉通路; 耦合在所述输入和所述上拉路径之间以激活所述上拉路径的第一晶体管; 耦合在输入和下拉路径之间以激活下拉路径的第二晶体管; 以及用于保护上拉路径免受过电压的第三晶体管。输入缓冲器电路可以被配置为防止多个晶体管中的每一个上的过电压状态，并且输入缓冲器电路可以被配置为允许热插拔操作。

2. 发明授权

US07430137B2 Non-volatile memory cells in a field programmable gate array 失效
标题翻译：现场可编程门阵列中的非易失性存储单元
公开(公告)号：US07430137B2
公开(公告)日：2008-09-30
申请号：US11868694
申请日：2007-10-08
申请人： Jonathan W. Greene , Fethi Dhaoui , Robert M. Salter, III , John McCollum
发明人： Jonathan W. Greene , Fethi Dhaoui , Robert M. Salter, III , John McCollum
IPC分类号： G11C16/02 , G11C5/02 , G11C5/06 , G06F7/38 , H03K19/173 , H03K19/177 , H03K19/94
CPC分类号： H03K19/1776 , G11C16/0441 , H03K19/17736 , H03K19/1778
摘要： A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a source, a drain, and a gate, the drain of the first p-channel MOS transistor electrically coupled to the drain of the first floating gate transistor forming a first common node. A second p-channel MOS transistor has a source, a drain, and a gate, the first drain of the second p-channel MOS transistor electrically coupled to the drain of the second floating gate transistor forming a second common node, the gate of the second p-channel MOS transistor electrically coupled to the first common node, and the second common node electrically coupled to the gate of the first p-channel MOS transistor.
摘要翻译：非易失性存储单元包括具有电耦合到行线的源极，漏极和栅极的第一浮栅晶体管。第二浮栅晶体管具有电耦合到行线的源极，漏极和栅极。第一p沟道MOS晶体管具有源极，漏极和栅极，第一p沟道MOS晶体管的漏极电耦合到第一浮动栅极晶体管的漏极，形成第一公共节点。第二p沟道MOS晶体管具有源极，漏极和栅极，第二p沟道MOS晶体管的第一漏极电耦合到形成第二公共节点的第二浮栅晶体管的漏极，栅极电耦合到第一公共节点的第二P沟道MOS晶体管，以及电耦合到第一p沟道MOS晶体管的栅极的第二公共节点。

3. 发明授权

US5691653A Product term based programmable logic array devices with reduced control memory requirements 失效
标题翻译：基于产品术语的可编程逻辑阵列器件，具有降低的控制存储器要求
公开(公告)号：US5691653A
公开(公告)日：1997-11-25
申请号：US586087
申请日：1996-01-16
申请人： David Wolk Mendel
发明人： David Wolk Mendel
IPC分类号： H03K19/177 , H03K19/94 , H03K7/38
CPC分类号： H03K19/17708
摘要： The number of programmable control elements required in a programmable AND array for use in a product term based programmable logic array device is reduced by generally feeding only the true or complement of each input logic signal into the AND array on an associated main word line conductor. Auxiliary word line conductors are provided for those input logic signals that are required in both true and complement form. The number of auxiliary word line conductors is less than the number of main word line conductors, which can reduce the required number of programmable control elements as compared to a conventional programmable AND array in which both the true and complement of all input logic signals are fed into the array.
摘要翻译：通过将每个输入逻辑信号的真实或补码通常仅馈入相关联的主字线导体上的AND阵列，可减少用于基于产品项的可编程逻辑阵列器件中的可编程AND阵列中所需的可编程控制元件的数量。辅助字线导体被提供用于真实和补充形式所需的那些输入逻辑信号。辅助字线导体的数量小于主字线导体的数量，与传统的可编程AND阵列相比，可减少所需数量的可编程控制元件，其中所有输入逻辑信号的真和补两者均被馈送进入阵列。

4. 发明授权

US07466164B1 Method and apparatus for a configurable low power high fan-in multiplexer 有权
标题翻译：用于可配置低功率高风扇多路复用器的方法和装置
公开(公告)号：US07466164B1
公开(公告)日：2008-12-16
申请号：US11759426
申请日：2007-06-07
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： H03K19/94
CPC分类号： H03K19/0008 , H03K17/005
摘要： A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高风扇多路复用器（MUX）。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

5. 发明授权

US5986480A Multiple input zero power AND/NOR gate for use in a field programmable gate array (FPGA) 失效
标题翻译：用于现场可编程门阵列（FPGA）的多输入零电源AND / NOR门
公开(公告)号：US5986480A
公开(公告)日：1999-11-16
申请号：US996119
申请日：1997-12-22
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H03K19/00 , H03K19/94
CPC分类号： H03K19/0016
摘要： A zero power AND or NOR (AND/NOR) gate includes circuitry configured for use in a field programmable gate array (FPGA). The AND/NOR gate includes multiple driver circuits each receiving a single input of the AND/NOR gate, each driver circuit being connected by a NORCNTL line and a NOROUT line to a current switch circuit. The NOROUT line provides the output of the AND/NOR gate, while the NORCNTL line enables zero power operation. The driver circuits can be included in input/output buffers (IOBs), configurable logic blocks (CLBs), or other components throughout an FPGA to receive more inputs than typically provided to a single CLB. Each of the driver circuits includes a pull down transistor having a gate receiving an input signal (IN.sub.1 -IN.sub.N) of the AND/NOR gate, and having a source to drain path connecting the NOROUT line to Vss. The current switch circuit includes a current source and a current control transistor with a source to drain path connecting the current source to the NOROUT line, and a gate coupled by the NORCNTL line to the driver circuits. Additional circuitry in each of the driver circuits controls the NORCNTL line to enable the current control transistor to turn on for a predetermined period of time when an input signal (IN.sub.1 -IN.sub.N) is applied to a driver circuit to turn off its respective pull down transistor.
摘要翻译：零功率AND或NOR（AND / NOR）门包括配置用于现场可编程门阵列（FPGA）的电路。 AND / NOR门包括多个驱动器电路，每个驱动电路接收AND / NOR门的单个输入，每个驱动电路通过NORCNTL线和NOROUT线连接到电流开关电路。 NOROUT线提供AND / NOR门的输出，而NORCNTL线使能零功率运行。驱动器电路可以包含在输入/输出缓冲器（IOB），可配置逻辑块（CLB）或FPGA中的其他组件中，以接收比通常提供给单个CLB的更多输入。每个驱动器电路包括一个具有接收与/或门的输入信号（IN1-INN）的栅极并且具有将NOROUT线连接到Vss的源极到漏极路径的下拉晶体管。电流开关电路包括电流源和电流控制晶体管，其具有将电流源连接到NOROUT线的源极至漏极路径，以及由NORCNTL线耦合到驱动器电路的栅极。每个驱动器电路中的附加电路控制NORCNTL线，以使得当输入信号（IN1-INN）被施加到驱动器电路以使其相应的下拉晶体管截止时，电流控制晶体管导通预定时间段。

6. 发明授权

US07005891B2 Data transmission circuit for universal serial bus system 有权
公开(公告)号：US07005891B2
公开(公告)日：2006-02-28
申请号：US10113375
申请日：2002-03-29
申请人： Jae-Jum Lee
发明人： Jae-Jum Lee
IPC分类号： H03K19/94
CPC分类号： G06F13/4072 , H03K17/164 , H04L25/0272 , H04L25/028 , H04L25/0286
摘要： The data transmission circuit generates the first and second data signals that are transferred respectively to first and second data lines after delaying or expanding a rising edge or a falling edge of an externally supplied data input signal, so that a crossover voltage of the data signals is established in accordance with the USB standard V1.1.

7. 发明授权

US06897685B2 Differential data transmitter 失效
标题翻译：差分数据发射机
公开(公告)号：US06897685B2
公开(公告)日：2005-05-24
申请号：US10649734
申请日：2003-08-28
申请人： Kiyohito Sato
发明人： Kiyohito Sato
IPC分类号： H03K5/125 , H03K19/0175 , H04L25/02 , H03K19/94
CPC分类号： H04L25/0288 , H04L25/0278 , H04L25/0282 , H04L25/0292
摘要： A differential data transmitter includes a first pre-driver configured to receive a differential data signal, a delay circuit configured to receive the differential data signal in parallel with the first pre-driver, and output the differential data signal with a delay time, and a second pre-driver configured to receive an output signal from the delay circuit. The delay circuit is capable of changing the delay time in accordance with a control signal. An output driver is configured to receive first and second output signals from the first and second pre-drivers, and output a pre-emphasis waveform signal that corresponds to a subtraction signal between the first and second output signals.
摘要翻译：差分数据发送器包括被配置为接收差分数据信号的第一预驱动器，配置成与第一预驱动器并联接收差分数据信号的延迟电路，并以延迟时间输出差分数据信号，第二预驱动器被配置为从延迟电路接收输出信号。延迟电路能够根据控制信号改变延迟时间。输出驱动器被配置为从第一和第二预驱动器接收第一和第二输出信号，并且输出对应于第一和第二输出信号之间的减法信号的预加重波形信号。

8. 发明授权

US6133762A Family of logic circuits emploting mosfets of differing thershold voltages 失效
标题翻译：一系列逻辑电路使不同温度的mosfet均匀化
公开(公告)号：US6133762A
公开(公告)日：2000-10-17
申请号：US50402
申请日：1998-03-30
申请人： Anthony M. Hill , Uming Ko
发明人： Anthony M. Hill , Uming Ko
IPC分类号： H03K17/30 , H03K19/094 , H03K19/0948 , H03K19/096 , H03K19/173 , H03K19/94 , H03K19/175 , H03K19/96
CPC分类号： H03K19/09429 , H03K19/0948 , H03K19/0963 , H03K19/1738
摘要： This invention involves logic circuits formed of metal oxide semiconductor field effect transistors having differing threshold voltages. In a first embodiment, the logic circuit includes a first and a second series connection. The first series connection between a first supply voltage and an output node consists of a source-drain path of an N-channel transistor having a high threshold voltage and a pull-down conditional conduction path of a pull-down network constructed exclusively of transistors having a low threshold voltage. The second series connection between said supply voltage and said output node consists of a source-drain path of a P-channel transistor having the high threshold voltage and a pull-up conditional conduction path of a pull-up network constructed exclusively of transistors having the low threshold voltage. The two high threshold voltage MOSFETs receive at their respective gates inverse signals so that either both are conducting or both are off. The pull-down network and pull-up network each receives input signals which control whether they conduct. These input signals are preferably selected so that the pull-down network and pull-up network do not conduct simultaneously. The two parts of each series connection may be in either order. The first input signal is preferably a clock signal. The pull-down network is preferably constructed exclusively of N-channel transistors. The pull-up network is preferably constructed exclusively of P-channel transistors.
摘要翻译：本发明涉及由具有不同阈值电压的金属氧化物半导体场效应晶体管形成的逻辑电路。在第一实施例中，逻辑电路包括第一和第二串联连接。第一电源电压和输出节点之间的第一串联连接由具有高阈值电压的N沟道晶体管的源极 - 漏极路径和由仅由晶体管构成的下拉网络的下拉条件导电路径组成低阈值电压。所述电源电压和所述输出节点之间的第二串联连接包括具有高阈值电压的P沟道晶体管的源极 - 漏极路径和仅由具有该栅极电压的晶体管构成的上拉网络的上拉条件导通路径低阈值电压。两个高阈值电压MOSFET在其各自的门处接收反向信号，使得两者都导通或两者都断开。下拉网络和上拉网络每个接收控制它们是否进行的输入信号。优选地选择这些输入信号，使得下拉网络和上拉网络不同时进行。每个串联连接的两个部分可以是任一顺序。第一输入信号优选地是时钟信号。下拉网络优选地由N沟道晶体管构成。上拉网络优选地由P沟道晶体管构成。

9. 发明授权

US5973512A CMOS output buffer having load independent slewing 失效
标题翻译： CMOS输出缓冲器具有负载独立回转
公开(公告)号：US5973512A
公开(公告)日：1999-10-26
申请号：US982959
申请日：1997-12-02
申请人： Alan J. Baker
发明人： Alan J. Baker
IPC分类号： H03K19/003 , H03K19/03 , H03K19/94
CPC分类号： H03K19/00361
摘要： A buffer having an output slew rate which is relatively insensitive to loading and supply voltage. The output buffer includes an output node, a first half-circuit and a second half-circuit. The first half-circuit is for slewing the output node from a first voltage to a second voltage. The first half-circuit includes a first output transistor connected between the output node and a second voltage reference node, a first switching device connected from a gate of the first output transistor to the second voltage reference node, a second switching device connected from the gate of the output transistor to a first node, a first current source connected from a first voltage reference node to the first node, and a first capacitor connected from the output node to the first node. The second half-circuit is for slewing the output node from the second voltage to the first voltage. The second half-circuit includes a second output transistor connected between the output node and the first voltage reference node, a third switching device connected from the gate of the second output transistor to the first voltage reference node, a fourth switching device connected from the gate of the second output transistor to a second node, a second current source connected from the second voltage reference node to the second node, and a second capacitor connected from the output node to the second node.
摘要翻译： nA缓冲器具有对负载和电源电压相对不敏感的输出转换速率。输出缓冲器包括输出节点，第一半电路和第二半电路。第一半电路用于将输出节点从第一电压转换到第二电压。第一半电路包括连接在输出节点和第二参考节点之间的第一输出晶体管，从第一输出晶体管的栅极连接到第二参考电压的第一开关器件，从栅极连接的第二开关器件输出晶体管连接到第一节点，从第一电压参考节点连接到第一节点的第一电流源以及从输出节点连接到第一节点的第一电容器。第二半电路用于将输出节点从第二电压转换到第一电压。第二半电路包括连接在输出节点和第一参考电压节点之间的第二输出晶体管，从第二输出晶体管的栅极连接到第一参考电压的第三开关器件，从栅极连接的第四开关器件将第二输出晶体管连接到第二节点，从第二参考节点连接到第二节点的第二电流源，以及从输出节点连接到第二节点的第二电容器。

10. 发明授权

US5610535A Programmable two-line, two-phase logic array 失效
标题翻译：可编程双线，两相逻辑阵列
公开(公告)号：US5610535A
公开(公告)日：1997-03-11
申请号：US533990
申请日：1995-09-27
申请人： Akira Masaki , Makoto Kuwata , Ryuichi Satomura , Nobuo Tamba
发明人： Akira Masaki , Makoto Kuwata , Ryuichi Satomura , Nobuo Tamba
IPC分类号： G06F7/00 , H01L21/82 , H03K19/173 , H03K19/177 , H03K19/94 , H03K7/38
CPC分类号： H03K19/17704
摘要： A programmable two-line, two-phase logic array has a plurality of inputs, each having two input signals operating in two phases and memory cells provided at an intersection of the input signal lines and output lines corresponding to at least one function that cross the input lines. The memory cells are capable of being written in the fabrication process or by a field programming process that addresses the contact points at which the input and output lines cross. The two-line, two-phase logic circuit can be attained by the same technique as that used for attaining a conventional PLA without designing circuitry based on a conventional synchronous logic beforehand followed by replacing it with a two-line, two-phase circuit.
摘要翻译：可编程的双线两相逻辑阵列具有多个输入，每个输入具有在两相中工作的两个输入信号，并且提供在与输入信号线和输出线相对应的至少一个功能的交点处的存储单元输入线。存储器单元能够被写入制造过程中或通过现场编程处理来处理输入和输出线交叉的接触点。双线两相逻辑电路可以通过与用于实现常规PLA相同的技术获得，而不需要预先设计基于常规同步逻辑的电路，然后用双线两相电路替换它。

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