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1. 发明授权

US09069706B2 Confidential information protection system and method 有权
公开(公告)号：US09069706B2
公开(公告)日：2015-06-30
申请号：US12069713
申请日：2008-02-11
申请人： Parthasarathy Sriram , Gordon Grigor , Shu-Jen Fang
发明人： Parthasarathy Sriram , Gordon Grigor , Shu-Jen Fang
IPC分类号： H04L9/32 , H04L9/00 , G06F12/14 , G06F21/62
CPC分类号： G06F12/1416 , G06F12/1408 , G06F21/6218
摘要： Efficient and effective permission confidential information protection systems and methods are described. The secure information protection systems and methods facilitate storage of confidential information in a manner safe from rogue software access. In one embodiment, a confidential information protection method is implemented in hardware and facilitates protection against software and/or Operating System hacks. In one exemplary implementation, a confidential information protection method includes setting a permission sticky bit flag to a default state upon system set up. The permission sticky bit flag access permission indication is adjusted at system reset in accordance with an initial application instruction. Access to the confidential information is restricted in accordance with the permission sticky bit and the permission sticky bit is protected from adjustments attempting to violate the permission indication. For example, another software application can not access or alter confidential information (e.g., an encryption key, initialization vector, etc.) if a permission sticky bit is designated as the highest security rating (e.g., disabling read permission and write permission until system reset).

2. 发明授权

US08599841B1 Multi-format bitstream decoding engine 有权
标题翻译：多格式比特流解码引擎
公开(公告)号：US08599841B1
公开(公告)日：2013-12-03
申请号：US11392095
申请日：2006-03-28
申请人： Parthasarathy Sriram
发明人： Parthasarathy Sriram
IPC分类号： H04L12/28 , H04L12/50 , H04N7/12 , H04N11/02
CPC分类号： H04N19/42 , H04N19/44 , H04N19/91
摘要： Configurable bitstream engines are described that can operate to decode variable length decoding of video and audio bitstreams encoded using any of a plurality of encoding schemes. Systems and methods are described that allow functional components of a bitstream engine to be disabled, enabled and configured as necessitated by the encoding scheme used to encode a bitstream. Functional components of a bitstream engine can perform single actions and operations, repetitive actions and operations and sequences of actions and operations as desired. A bit field extraction process is described for extracting bit fields of specified length from memory, updating bit offsets, loading new data from memory when needed.
摘要翻译：描述了可配置比特流引擎，其可以操作以解码使用多种编码方案中的任何一种编码的视频和音频比特流的可变长度解码。描述了允许比特流引擎的功能组件被禁用，启用和配置的系统和方法，这是由用于编码比特流的编码方案所必需的。比特流引擎的功能组件可以根据需要执行单个动作和操作，重复动作和操作以及动作和操作序列。描述用于从存储器提取指定长度的位字段的位字段提取处理，更新位偏移，在需要时从存储器加载新数据。

3. 发明授权

US07884742B2 System and method for efficient compression of digital data 有权
标题翻译：数字数据有效压缩的系统和方法
公开(公告)号：US07884742B2
公开(公告)日：2011-02-08
申请号：US11422974
申请日：2006-06-08
申请人： Rohit Puri , Parthasarathy Sriram
发明人： Rohit Puri , Parthasarathy Sriram
IPC分类号： H03M7/40
CPC分类号： H04N19/91 , H04N19/103 , H04N19/105 , H04N19/124 , H04N19/129 , H04N19/46 , H04N19/60 , H04N19/70
摘要： A system for compressing digital data by representing a portion of it predictionally and transformationally as a block of transform coefficients, then quantizing that block selectively into a set of encoding symbols based on an indication whether the transform coefficients represent the portion as having a particular characteristic, and then by encoding the set of encoding symbols into a data bit stream. In particular, frequency may be used as the characteristic of the digital data in many applications.
摘要翻译：一种用于通过将数据数据预先和变换地表示为变换系数块来压缩数字数据的系统，然后基于变换系数是否表示该部分具有特定特征的指示将该块有选择地量化到一组编码符号中，然后通过将该组编码符号编码成数据比特流。特别地，频率可以用作许多应用中数字数据的特征。

4. 发明申请

US20090204835A1 USE METHODS FOR POWER OPTIMIZATION USING AN INTEGRATED CIRCUIT HAVING POWER DOMAINS AND PARTITIONS 审中-公开
标题翻译：使用具有电源域和分区的集成电路的电源优化的使用方法
公开(公告)号：US20090204835A1
公开(公告)日：2009-08-13
申请号：US12029442
申请日：2008-02-11
申请人： Brian Smith , Parthasarathy Sriram , Stephane Le Provost
发明人： Brian Smith , Parthasarathy Sriram , Stephane Le Provost
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： In a programmable SoC (system-on-a-chip) integrated circuit device, a method for optimizing power efficiency for a requested device functionality. The method includes determining a requested device functionality, and in response to the requested device functionality, turning on power for a selected one or more power domains out of a plurality of power domains included within the integrated circuit device. Each of the power domains has its own respective voltage rail to obtain power. The method further includes turning on one or more power islands out of a plurality of power islands included within the integrated circuit device. The requested device functionality is then implemented using one or more functional blocks wherein each functional block is configured to provide a specific device functionality.
摘要翻译：在可编程SoC（片上系统）集成电路器件中，一种用于优化所请求的器件功能的功率效率的方法。该方法包括确定所请求的设备功能，以及响应于所请求的设备功能，为包括在集成电路设备内的多个电力域中的所选择的一个或多个电力域开启电力。每个电源域具有各自的电压轨以获得电力。该方法还包括将包含在集成电路器件内的多个功率岛中的一个或多个功率岛接通。然后使用一个或多个功能块来实现所请求的设备功能，其中每个功能块被配置为提供特定的设备功能。

5. 发明申请

US20090204830A1 POWER MANAGEMENT WITH DYNAMIC FREQUENCY DAJUSTMENTS 有权
标题翻译：电力管理与动态频率调节
公开(公告)号：US20090204830A1
公开(公告)日：2009-08-13
申请号：US12029375
申请日：2008-02-11
申请人： Aleksandr Frid , Parthasarathy Sriram
发明人： Aleksandr Frid , Parthasarathy Sriram
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3228 , G06F1/324 , Y02D10/126
摘要： A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode.
摘要翻译：中央处理单元（CPU）可以指定用于由设备执行任务的时钟信号的初始（例如基线）频率。然后将CPU置于降低功率模式。在CPU处于降低功耗模式之后，器件执行任务，直到触发事件导致器件向CPU发送中断为止。响应中断，CPU唤醒动态调整时钟频率。如果时钟频率重置为基准值，则CPU将再次处于降低功耗模式。

6. 发明授权

US06272175B1 Video signal coding systems and processes using adaptive quantization 失效
标题翻译：视频信号编码系统和使用自适应量化的处理
公开(公告)号：US06272175B1
公开(公告)日：2001-08-07
申请号：US08799995
申请日：1997-02-13
申请人： Parthasarathy Sriram , Anurag Bist
发明人： Parthasarathy Sriram , Anurag Bist
IPC分类号： H04B166
CPC分类号： H04N19/18 , H04N19/126 , H04N19/146 , H04N19/147 , H04N19/149 , H04N19/154 , H04N19/172 , H04N19/60
摘要： A compression system and process employs a group of quantizers (or sets of predefined quantized values) and involes the selection of the quantizers for each video frame or frame portion. For each frame portion, a selection of the most appropriate quantizer is made. The selection of which quantizer from the selection group is most appropriate for coding of a video frame or frame portion is based on a formula which takes into account both the distortion (accuracy) and bit rate characteristics of each quantizer. The quantizer that exhibits the best combined distortion and bit rate characteristics is selected for coding the frame or frame portion. A similar formula, based on both distortion and bit rate characteristics, is used to select the particular quantization value within the quantizer set for each video signal value being coded.
摘要翻译：压缩系统和过程采用一组量化器（或预定义的量化值集合），并且涉及每个视频帧或帧部分的量化器的选择。对于每个帧部分，进行最合适的量化器的选择。来自选择组的哪个量化器的选择最适合于视频帧或帧部分的编码是基于考虑了每个量化器的失真（精度）和比特率特性两者的公式。选择具有最佳组合失真和比特率特性的量化器来对帧或帧部分进行编码。基于失真和比特率特性的类似公式用于为正被编码的每个视频信号值选择量化器集合内的特定量化值。

7. 发明授权

US08370663B2 Power management with dynamic frequency adjustments 有权
标题翻译：电源管理采用动态频率调节
公开(公告)号：US08370663B2
公开(公告)日：2013-02-05
申请号：US12029375
申请日：2008-02-11
申请人： Aleksandr Frid , Parthasarathy Sriram
发明人： Aleksandr Frid , Parthasarathy Sriram
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3228 , G06F1/324 , Y02D10/126
摘要： A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode.
摘要翻译：中央处理单元（CPU）可以指定用于由设备执行任务的时钟信号的初始（例如基线）频率。然后将CPU置于降低功率模式。在CPU处于降低功耗模式之后，器件执行任务，直到触发事件导致器件向CPU发送中断为止。响应中断，CPU唤醒动态调整时钟频率。如果时钟频率重置为基准值，则CPU将再次处于降低功耗模式。

8. 发明申请

US20090201082A1 INTEGRATED CIRCUIT DEVICE HAVING POWER DOMAINS AND PARTITIONS BASED ON USE CASE POWER OPTIMIZATION 有权
标题翻译：基于使用电源优化的具有电源域和分区的集成电路设备
公开(公告)号：US20090201082A1
公开(公告)日：2009-08-13
申请号：US12029404
申请日：2008-02-11
申请人： Brian Smith , Parthasarathy Sriram , Stephane Le Provost
发明人： Brian Smith , Parthasarathy Sriram , Stephane Le Provost
IPC分类号： G05F1/10
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands.
摘要翻译：具有优化的电源域和电源岛的可编程SoC（片上系统）。 SoC是包括多个功率域的集成电路器件，每个电源域具有相应的电压轨，以向电源域供电。多个功率岛包括在集成电路器件内，其中每个功率域包括至少一个功率岛。多个功能块包括在集成电路器件内，其中每个功率岛包括至少一个功能块。每个功能块被配置为提供特定的设备功能。集成电路装置通过单独打开或关闭所选择的一个或多个功率域的功率来调整与所请求的装置功能相关的功率消耗，并且对于每个打开的功率域，单独地对一个或多个功率岛进行供电。

9. 发明授权

US06654419B1 Block-based, adaptive, lossless video coder 有权
标题翻译：基于块的自适应无损视频编码器
公开(公告)号：US06654419B1
公开(公告)日：2003-11-25
申请号：US09561299
申请日：2000-04-28
申请人： Parthasarathy Sriram , Subramania Sudharsanan
发明人： Parthasarathy Sriram , Subramania Sudharsanan
IPC分类号： H04N718
CPC分类号： H04N19/507 , H04N19/105 , H04N19/136 , H04N19/174 , H04N19/18 , H04N19/436 , H04N19/46 , H04N19/51 , H04N19/61 , H04N19/91
摘要： Method and system for compression coding of a digitally represented video image. The video image is expressed as one or more data blocks in two or more frames, each block having a sequence of pixels with pixel values. Within each block of a frame, an intra-frame predictor index or inter-frame predictor index is chosen that predicts a pixel value as a linear combination of actual pixel values, drawn from one frame or from two or more adjacent frames. The predicted and actual pixel values are compared, and twice the predicted value is compared with the sum of the actual value and a maximum predicted value, to determine a value index, which is used to represent each pixel value in a block in compressed format in each frame. The compression ratios achieved by this coding approach compare favorably with, and may improve upon, the compression achieved by other compression methods. Several processes in determination of the compressed values can be performed in parallel to increase throughput or to reduce processing time.
摘要翻译：用于数字化视频图像的压缩编码的方法和系统。视频图像被表示为两个或更多个帧中的一个或多个数据块，每个块具有带有像素值的像素序列。在帧的每个块内，选择帧内预测器索引或帧间预测器索引，其将像素值预测为从一个帧或两个或更多个相邻帧绘制的实际像素值的线性组合。比较预测值和实际像素值，将预测值与实际值和最大预测值的和进行比较，以确定用于以压缩格式表示块中的每个像素值的值索引每一帧。通过该编码方法实现的压缩比与其它压缩方法实现的压缩有利地相比并且可以改进。可以并行执行确定压缩值的几个过程，以增加吞吐量或减少处理时间。

10. 发明授权

US6043844A Perceptually motivated trellis based rate control method and apparatus for low bit rate video coding 失效
标题翻译：用于低比特率视频编码的感知动机的网格速率控制方法和装置
公开(公告)号：US6043844A
公开(公告)日：2000-03-28
申请号：US802042
申请日：1997-02-18
申请人： Anurag Bist , Parthasarathy Sriram
发明人： Anurag Bist , Parthasarathy Sriram
IPC分类号： H04N7/26 , G06T9/00 , H03M7/30 , H04N7/50 , H04N7/12
CPC分类号： G06T9/008 , H04N19/126 , H04N19/137 , H04N19/147 , H04N19/149 , H04N19/172 , H04N19/176 , H04N19/61 , H04N19/146 , H04N19/152
摘要： A method and apparatus for compressing and transmitting variable amounts of video data in real time over a channel having a fixed bandwidth. A trellis having a plurality of nodes is provided. Each of the plurality of nodes has an associated quantization parameter and bit number. The bit number associated with each node corresponds to a quantity of bits consumed in reaching that node. For each of the plurality of blocks, a minimum path through the trellis is selected. A quantization parameter associated with the selected minimum path is selected. A number of bits is assigned to each of the plurality of blocks in accordance with the selected quantization parameter. A substantially fixed number of bits is distributed among the plurality of blocks which make up each of the plurality of frames in accordance with the selected quantization parameter. The number of bits per frame is substantially constant for each of the plurality of frames, and the distribution of bits within each of the plurality of frames varies in accordance with the content of the frame.
摘要翻译：一种用于在具有固定带宽的信道上实时压缩和发送可变量的视频数据的方法和装置。提供了具有多个节点的网格。多个节点中的每一个具有相关联的量化参数和比特数。与每个节点相关联的比特数对应于到达该节点消耗的比特数。对于多个块中的每个块，选择通过网格的最小路径。选择与所选择的最小路径相关联的量化参数。根据所选择的量化参数，将多个比特分配给多个块中的每一个。根据所选择的量化参数，在构成多个帧中的每一个的多个块之间分布实质上固定数量的比特。每帧的比特数对于多个帧中的每一个基本上是恒定的，并且多个帧中的每一帧内的比特的分布根据帧的内容而变化。

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