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    • 3. 发明授权
    • Communication system and method using asynchronous and isochronous
spectrum for voice and data
    • 用于语音和数据的异步和等时频谱通信系统和方法
    • US6011784A
    • 2000-01-04
    • US769026
    • 1996-12-18
    • David L. BrownPaul D. MarkoJaime A. Borras
    • David L. BrownPaul D. MarkoJaime A. Borras
    • H04L12/28H04J3/24
    • H04W74/02H04W48/08H04W72/0446
    • In a time division, multiple access system, a base station (102) transmits an isochronous beacon (404, 422) at the start of each frame (400), conveying control and timing information. Following the isochronous beacon (404), isochronous time slots (414, 416, 418, 420) are dynamically allocated for communication of isochronous data. After communication of the isochronous data, the remainder of the frame (400) before the next isochronous beacon (422) is used for transmission of packets of asynchronous data. This technique gives priority to the isochronous data, which is real time, while also maximizing the bandwidth allocated for asynchronous data. A single transmitter circuit (124, 158) and receiver circuit (122, 156) at each station are used for communication of both isochronous data and asynchronous data.
    • 在时分多址接入系统中,基站(102)在每帧开始时发送等时信标(404,422),传送控制和定时信息。 在等时信标(404)之后,动态分配同步时隙(414,416,418,420)用于同步数据的通信。 在同步数据通信之后,在下一个同步信标(422)之前的帧(400)的剩余部分被用于异步数据分组的传输。 这种技术优先考虑实时的同步数据,同时最大化分配给异步数据的带宽。 每个站处的单个发射机电路(124,158)和接收机电路(122,156)用于同步数据和异步数据的通信。
    • 5. 发明授权
    • Multi-mode digital phase lock loop
    • 多模数字锁相环
    • US5436937A
    • 1995-07-25
    • US11926
    • 1993-02-01
    • David L. BrownPaul D. Marko
    • David L. BrownPaul D. Marko
    • H03L7/08H03L7/099H04L7/033H03D3/24
    • H03L7/0992H03L7/08H04L7/0331
    • A multi-mode PLL circuit (100) includes an early/late bit transition accumulator (108) for accumulating the number of incoming bit transitions which are early or late. This allows for PLL (100) to provide adjustments based on a predetermined number of accumulated early/late accumulations or based on an average of early/late transitions over a predetermined period of time. PLL (100) further includes a frequency offset circuit (200) which includes a frequency error accumulator which is used to maintain a frequency offset history and to control the loop frequency. This allows for very narrow band operation of the first order digital PLL while maintaining stable operation.
    • 多模式PLL电路(100)包括用于累加早期或晚期的输入位转换次数的早/晚位转换累加器(108)。 这允许PLL(100)基于预定数量的累加的早/晚累积或者基于在预定时间段内的早/晚转换的平均值来提供调整。 PLL(100)还包括频率偏移电路(200),其包括用于维持频率偏移历史并控制环路频率的频率误差累加器。 这允许一阶数字PLL的非常窄的频带操作,同时保持稳定的操作。
    • 7. 发明授权
    • Nested digital phase lock loop
    • 嵌套数字锁相环
    • US5463351A
    • 1995-10-31
    • US314830
    • 1994-09-29
    • Paul D. MarkoCraig P. WadinDavid L. Brown
    • Paul D. MarkoCraig P. WadinDavid L. Brown
    • H03L7/06H03L7/07H03L7/099H04L7/00H04L7/033H03L7/10
    • H03L7/07H03L7/0991H04L7/0004H04L7/033
    • A nested digital phase lock loop (DPLL) circuit (400) provides center bit sampling for incoming recovered data (406). Included in the nested DPLL circuit (400) are a narrow bandwidth DPLL (402) and a wide bandwidth DPLL (404) which generate first (410) and second (428) recovered clock signals respectively. Initially the first recovered clock signal (410) is used to clock in the recovered data (406) until the narrowband DPLL (402) is stabilized. Once the narrowband DPLL (402) is stabilized, the second recovered clock signal (428) generated from the wideband DPLL (404) is switched in by a multiplexer (424). If for any reason the center bit sampled data becomes corrupted, a RESET occurs in the wideband loop (404) to zero out the phase shift of the second recovered clock signal (428) to match that of the narrow loop. Thus, when a RESET occurs, the wideband loop is tracking at exactly the same clock rate as the narrowband loop.
    • 嵌套数字锁相环(DPLL)电路(400)为输入的恢复数据(406)提供中心位采样。 包含在嵌套DPLL电路(400)中的是窄带宽DPLL(402)和宽带宽DPLL(404),其分别产生第一(410)和第二(428)恢复的时钟信号。 最初,第一恢复时钟信号(410)用于在恢复的数据(406)中进行时钟,直到窄带DPLL(402)稳定为止。 一旦窄带DPLL(402)稳定,则从宽带DPLL(404)产生的第二恢复时钟信号(428)被多路复用器(424)切换。 如果由于任何原因,中心位采样数据被破坏,则在宽带环路(404)中发生复位以将第二恢复时钟信号(428)的相移清零以匹配窄环路的相移。 因此,当发生RESET时,宽带环路跟窄带环路完全相同的时钟速率进行跟踪。
    • 8. 发明授权
    • Method and apparatus for synchronization in a wireless telephone system
    • 无线电话系统中同步的方法和装置
    • US5384828A
    • 1995-01-24
    • US136846
    • 1993-10-18
    • David L. BrownMotjaba AghaalianPaul D. Marko
    • David L. BrownMotjaba AghaalianPaul D. Marko
    • H04L7/04H04L7/10H04M1/725H04M11/00
    • H04M1/72505H04L7/042H04L7/10
    • A resynchronization method for use in a communication system, such as a second generation cordless telephone system 800, begins by determining that synchronization has been lost by a receiving unit (830). The receiving unit than mutes any transmit data and generates zero data which is combined with a pattern generated by pattern generator (812). The transmission is then received by handset (830), which detects the pattern generated by pattern generator (812) using pattern detector (850). Pattern detector (850) then generates a pattern detected signal (852) which causes handset (840) to also stop sending data and generate a pattern accompanied by zero data. Base station (830) detects the pattern and again generates another pattern accompanied with zero data which is transmitted to handset (840). Handset (840) after decoding the pattern for the second time begins to resumes the normal transmission of data to base station (830).
    • 用于诸如第二代无绳电话系统800的通信系统中的再同步方法通过确定接收单元(830)已经失去同步而开始。 接收单元使任何发送数据静音,并产生与由模式发生器(812)生成的模式组合的零数据。 然后由手持机(830)接收传输,手机(830)使用模式检测器(850)检测由模式发生器(812)产生的模式。 模式检测器(850)然后产生模式检测信号(852),其使手机(840)也停止发送数据并产生伴随零数据的模式。 基站(830)检测模式,并再次产生伴随零数据的另一模式,该数据被发送到手机(840)。 在第二次解码模式之后的手机(840)开始恢复到基站的数据的正常传输(830)。
    • 10. 发明授权
    • Bedbug infestation-resistant bed
    • 虫蛀抗虫床
    • US08739333B2
    • 2014-06-03
    • US12798497
    • 2010-04-05
    • Michelle BoyleDavid L. Brown
    • Michelle BoyleDavid L. Brown
    • A47C19/00
    • A47C19/024A47C19/021A47C27/14A47G9/0292
    • A bedbug-resistant bed comprises a horizontal right-rectangular frame including four open angled rigid members pair-wise joined at their eight termini in four corners; one or more support members extending across the frame near the upper edge of the joined angled members; and a right-rectangular wire mesh infill expanse extending within a perimeter of the frame and affixed along upper inwardly extending expanses of the joined angled members. A bedbug-resistant bed in another embodiment comprises two right-rectangular horizontal frames differentially dimensioned in three orthogonal axes such that one of the two frames is fittable within a three-dimensional enclosure defined by the other of the two frames for stowage of the bed, the two frames configured in deployment in a proximate side by side arrangement, each frame including four open angled rigid members joined at their eight termini to define a perimeter and four corners of the frame, each frame further including one or more solid support members extending across the frame, and each frame further including four legs extending downwardly from the four corners of the frame.
    • 防虫床包括一个水平的右矩形框架,包括四个开放角度的刚性构件,它们在四个角落的八个端部成对连接; 一个或多个支撑构件在接合的成角度构件的上边缘附近延伸穿过框架; 并且在框架的周边内延伸并沿着连接的倾斜构件的上部向内延伸的宽度固定的正方形的丝网填充物。 在另一实施例中的防虫床包括两个在三个正交轴线上有差异尺寸的右矩形水平框架,使得两个框架中的一个框架可装配在由两个框架中的另一个框架限定的三维外壳中,用于存放床, 两个框架被构造为以邻近的并排配置展开,每个框架包括四个开口成角度的刚性构件,其在其八个端部处连接以限定框架的周边和四个角部,每个框架还包括一个或多个贯穿 框架,并且每个框架还包括从框架的四个角落向下延伸的四个腿。