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1. 发明授权

US5586306A Integrated circuit servo system control for computer mass storage device with distributed control functionality to reduce transport delay 失效
标题翻译：用于具有分布式控制功能的计算机大容量存储设备的集成电路伺服系统控制，以减少传输
公开(公告)号：US5586306A
公开(公告)日：1996-12-17
申请号：US448098
申请日：1995-05-23
申请人： Paul M. Romano , Larry D. King , John S. Geldman , Bhupendra K. Ahuja , Palaksha Setty , Petro Estakhri , Son Ho , Phuc Tran , Maryam Imam
发明人： Paul M. Romano , Larry D. King , John S. Geldman , Bhupendra K. Ahuja , Palaksha Setty , Petro Estakhri , Son Ho , Phuc Tran , Maryam Imam
IPC分类号： G11B5/55 , G11B5/596 , G11B19/02 , G11B19/12 , G11B19/20 , G11B19/28 , G11B20/10 , G11B21/08 , G11B21/10 , G11B27/30 , G11B33/10 , G06F3/00
CPC分类号： G11B27/3027 , G11B19/02 , G11B19/12 , G11B19/20 , G11B19/28 , G11B20/10 , G11B21/083 , G11B21/106 , G11B5/5526 , G11B5/59605 , G11B5/59655 , G11B33/10
摘要： An integrated circuit controls the low level, electromechanical functionality of a computer mass storage device, such as a magnetic disk drive incorporating a spindle motor for rotatably controlling a disk and an actuator for positioning at least one read/write head with respect to the disk, to read or write encoded data configured in information data sectors and to sense encoded data of servo data sectors. A servo subsystem is coupled to an output of the read/write head for detecting the servo data sectors and providing a control signal in response thereto. An analog-to-digital subsystem is also coupled to an output of the read/write head and is operative in response to the servo subsystem control signal for converting the encoded data of the servo data sectors to digital transducer position information representative of a position of the read/write head with respect to the data tracks. A data processing subsystem is coupled to the analog-to-digital subsystem for processing the digital transducer position information and providing digital motion control signals in response thereto. A digital-to-analog subsystem is coupled to the data processing subsystem for providing analog control signals to the spindle motor and the actuator in response to the digital motion control signals.
摘要翻译：集成电路控制计算机大容量存储装置的低级机电功能，例如包括用于可旋转地控制盘的主轴电机的磁盘驱动器和用于相对于盘定位至少一个读/写头的致动器，读取或写入配置在信息数据扇区中的编码数据，并读取伺服数据扇区的编码数据。伺服子系统耦合到读/写头的输出端，用于检测伺服数据扇区并提供响应于此的控制信号。模拟数字子系统还耦合到读/写头的输出端，并响应于伺服子系统控制信号操作，用于将伺服数据扇区的编码数据转换为数字换能器位置信息，该位置信息表示相对于数据轨道的读/写头。数据处理子系统耦合到模数 - 数字子系统，用于处理数字换能器位置信息并响应于此提供数字运动控制信号。数字到模拟子系统耦合到数据处理子系统，用于响应于数字运动控制信号向主轴电动机和致动器提供模拟控制信号。

2. 发明授权

US5576910A Burst comparison and sequential technique for determining servo control in a mass storage disk device 失效
标题翻译：用于确定大容量存储盘装置中的伺服控制的突发比较和顺序技术
公开(公告)号：US5576910A
公开(公告)日：1996-11-19
申请号：US441676
申请日：1995-05-15
申请人： Paul M. Romano , Larry D. King , Mike Machado , Petro Estakhri , Son Ho , Phuc Tran , Maryam Imam
发明人： Paul M. Romano , Larry D. King , Mike Machado , Petro Estakhri , Son Ho , Phuc Tran , Maryam Imam
IPC分类号： G11B5/596
CPC分类号： G11B5/59655
摘要： A burst magnitude comparator and an instruction sequencer are employed in a servo system controller to rapidly determine position correction information for moving a transducer head over the center line of a track recorded on a disk in a mass storage disk drive. The burst magnitude comparator selects at least two burst signals derived from bursts recorded at predetermined locations relative to the center line from which to derive a correction control signal, based on a predetermined relationship of the burst signals, and supplies the selected burst signals in a predetermined order to facilitate calculation of the correction signal by a data processor used with the servo system controller. An instruction sequencer controls a sequence of converting the analog burst signals from the head to digital burst signals without intervention or control from the data processor. By ordering the signals with the burst magnitude comparator and by sequencing the conversion of the signals, the calculation is speeded and the processing and code requirements for the data processor are greatly reduced, thereby reducing transport delay and freeing the resources of the processor for use in other, potentially more important tasks associated with the servo controller.
摘要翻译：在伺服系统控制器中采用脉冲串幅度比较器和指令定序器来快速地确定位置校正信息，用于将传感器头移动到记录在大容量存储盘驱动器中的盘上的轨道的中心线上。脉冲串幅度比较器基于脉冲串信号的预定关系，从相对于中心线记录的脉冲串中选出至少两个突发信号，并将其提供给预定的脉冲信号为了便于利用伺服系统控制器使用的数据处理器来计算校正信号。指令定序器控制从头到数字突发信号转换模拟脉冲串信号的顺序，而不需要来自数据处理器的干预或控制。通过用脉冲串幅度比较器排序信号并对信号的转换进行排序，计算速度加快，数据处理器的处理和编码要求大大降低，从而减少了传输延迟并释放了处理器的资源，用于与伺服控制器相关的其他可能更重要的任务。

3. 发明授权

US5477103A Sequence, timing and synchronization technique for servo system controller of a computer disk mass storage device 失效
标题翻译：计算机磁盘大容量存储设备的伺服系统控制器的顺序，定时和同步技术
公开(公告)号：US5477103A
公开(公告)日：1995-12-19
申请号：US72135
申请日：1993-06-04
申请人： Paul M. Romano , Larry D. King , Mike Machado , Petro Estakhri , Son Ho , Phuc Tran , Maryam Imam
发明人： Paul M. Romano , Larry D. King , Mike Machado , Petro Estakhri , Son Ho , Phuc Tran , Maryam Imam
IPC分类号： G11B19/12 , G11B19/28 , G05B19/29
CPC分类号： G11B19/28 , G11B19/12
摘要： A servo system controller for a disk drive device which includes a rotating mass storage disk incorporates a timing error determining circuit for determining rotational speed variations in the disk from information contained in a servo field recorded in a track. A timing error signal is supplied when the speed variation exceeds a threshold, thus indicating an unacceptable level of speed variation. A digital synchronizer responds to asynchronous servo data signals from the disk to establish a cell clock signal occurring about a normal frequency, a cell during which only one servo data signal will occur, and a cell data signal which occurs during the cell. The cell clock signal clocks logical operations on a synchronous basis, and servo data signals are reliably captured. A concurrence determining circuit determines the degree of concurrence between the predetermined series of cell data signals and an actual pattern of signals derived from the servo field, and recognizes the servo control information from less than complete concurrence of the derived pattern and the actual expected pattern. Normal operation is permitted even through slight inconsistences may be detected, improving data throughput while still achieving an adequate level of error tolerance.
摘要翻译：一种包括旋转大容量存储盘的磁盘驱动装置的伺服系统控制器包括一个定时误差确定电路，用于根据记录在磁道中的伺服磁场中包含的信息确定磁盘的转速变化。当速度变化超过阈值时提供定时误差信号，从而指示不可接受的速度变化水平。数字同步器响应于来自盘的异步伺服数据信号，以建立围绕正常频率发生的单元时钟信号，即仅将发生一个伺服数据信号的单元以及在单元期间发生的单元数据信号。单元时钟信号在同步的基础上对逻辑运算进行时钟运算，并可靠地捕获伺服数据信号。同步确定电路确定预定的一系列单元数据信号与从伺服磁场导出的实际信号模式之间的并发程度，并且从导出图案和实际期望图案的完全同意中识别伺服控制信息。即使可以检测到轻微的不一致，允许正常操作，提高数据吞吐量，同时仍能达到足够的容错水平。

4. 发明授权

US5502696A CD-ROM subcode R-W channel de-interleaving and de-scrambling method and apparatus 失效
标题翻译： CD-ROM子码R-W信道解交织和去加扰方法和装置
公开(公告)号：US5502696A
公开(公告)日：1996-03-26
申请号：US311069
申请日：1994-09-23
申请人： Tony J. Yoon , Michael J. McGrath , Phuc Tran
发明人： Tony J. Yoon , Michael J. McGrath , Phuc Tran
IPC分类号： G11B27/10 , G11B27/30 , G11B17/22
CPC分类号： G11B27/3063 , G11B27/105 , G11B2220/213 , G11B2220/2545
摘要： A subcode R-W channel data de-interleaving and de-scrambling method and apparatus includes the ability to de-interleave and de-scramble the encoded subchannel data without the necessity of storage elements, by dynamically calculating the final location of each byte of data within a packet as it is read from the CD-Rom. A pack counter monitors the pack number of the current byte of data. An index counter monitors the location of the current data within a pack. A subtractor uses the values from the pack counter and the index counter to obtain an input value, a first portion of which is supplied to a first offset generator. A second portion of the subtractor output is used to select a base address. The first offset generator determines the pack number of the current byte of data after the de-interleave process. A second offset generator receives a value from the index counter and generates a corresponding value. The results from the first offset generator and the second offset generator are both input into a first adder. The output of the first adder is added to the selected base address by a second adder in order to calculate the final address. The final address is transmitted with the current byte of data to an external buffer memory, where it is stored in the specified address. Preferably the present invention is included in a dedicated integrated circuit which calculates the final address of each byte of subchannel R-W data as it is read.
摘要翻译：子码RW信道数据解交织和去加扰方法和装置包括通过动态地计算数据的每个字节的最终位置，来对编码的子信道数据进行解交织和去加扰，而不需要存储元件包从CD-ROM读取。包计数器监视当前数据字节的包数。索引计数器监视包中当前数据的位置。减法器使用来自包计数器和索引计数器的值来获得输入值，其输入值的第一部分被提供给第一偏移发生器。减法器输出的第二部分用于选择基地址。第一个偏移生成器确定解交织处理后的数据的当前字节的包数。第二偏移生成器从索引计数器接收值并生成相应的值。来自第一偏移发生器和第二偏移发生器的结果都被输入到第一加法器。第一加法器的输出由第二加法器添加到所选择的基地址，以便计算最终地址。最终地址与当前数据字节一起发送到外部缓冲存储器，存储在指定的地址中。优选地，本发明被包括在专用集成电路中，该集成电路在读取时计算子信道R-W数据的每个字节的最终地址。

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