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1. 发明申请

US20090315119A1 CMOS CIRCUITS SUITABLE FOR LOW NOISE RF APPLICATIONS 有权
标题翻译： CMOS电路适用于低噪声RF应用
公开(公告)号：US20090315119A1
公开(公告)日：2009-12-24
申请号：US12306935
申请日：2007-06-27
申请人： Paul Ronald Stribley , John Nigel Ellis
发明人： Paul Ronald Stribley , John Nigel Ellis
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L27/0928
摘要： A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type diffusions, and those diffusions are contained within a deeper n-type diffusion, used to junction isolate components within the deeper n-type diffusion from components outside of the deeper n-type diffusion.
摘要翻译： CMOS电路包括在同一衬底上具有n型和p型栅极的CMOS MOSFET，其中衬底被分为n型和p型扩散区域，并且这些扩散包含在更深的n型扩散中，用于将更深的n型扩散的深部n型扩散中的组分隔离成较深的n型扩散。

2. 发明申请

US20090315080A1 TRANSISTOR ARRAY WITH SHARED BODY CONTACT AND METHOD OF MANUFACTURING 有权
标题翻译：具有共享身体接触的晶体管阵列和制造方法
公开(公告)号：US20090315080A1
公开(公告)日：2009-12-24
申请号：US12306947
申请日：2007-06-29
申请人： Paul Ronald Stribley , John Nigel Ellis
发明人： Paul Ronald Stribley , John Nigel Ellis
IPC分类号： H01L27/092 , H01L27/088 , H01L29/78
CPC分类号： H01L27/0203 , H01L21/823425 , H01L27/0705 , H01L27/0921 , H01L29/4238 , H01L29/78
摘要： An array of transistors arranged next to each other on a semiconductor material forming a substrate, the substrate comprising p-well or n-well diffusions forming a body, which diffusions are used as the body regions of the transistors, each transistor comprising a source, a drain and a gate, wherein the array of transistors further comprises at least one electrical connection to the body, wherein said electrical connection is shared by at least two transistors of said array. Also disclosed is a semiconductor device comprising at least one source, at least one drain, at least one gate between the at least one source and the at least one drain, and at least one structure of the same material as the at least one gate which does not have a connection means for electrical connection to the at least one gate.
摘要翻译：在形成衬底的半导体材料上彼此相邻布置的晶体管阵列，所述衬底包括形成体的p阱或n阱扩散，所述扩散用作晶体管的体区，每个晶体管包括源极，漏极和栅极，其中所述晶体管阵列还包括与所述主体的至少一个电连接，其中所述电连接由所述阵列的至少两个晶体管共享。还公开了一种半导体器件，其包括至少一个源极，至少一个漏极，至少一个源极与至少一个漏极之间的至少一个栅极，以及与该至少一个栅极相同的材料的至少一个结构，没有用于与至少一个门的电连接的连接装置。

3. 发明授权

US09947662B2 CMOS circuits suitable for low noise RF applications 有权
公开(公告)号：US09947662B2
公开(公告)日：2018-04-17
申请号：US12306935
申请日：2007-06-27
申请人： Paul Ronald Stribley , John Nigel Ellis
发明人： Paul Ronald Stribley , John Nigel Ellis
IPC分类号： H01L21/02 , H01L27/092
CPC分类号： H01L27/092 , H01L27/0928
摘要： A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type diffusions, and those diffusions are contained within a deeper n-type diffusion, used to junction isolate components within the deeper n-type diffusion from components outside of the deeper n-type diffusion.

4. 发明申请

US20100059851A1 CMOS CIRCUITS COMBINING HIGH VOLTAGE AND RF TECHNOLOGIES 审中-公开
标题翻译： CMOS电路组合高压和射频技术
公开(公告)号：US20100059851A1
公开(公告)日：2010-03-11
申请号：US12306952
申请日：2007-06-27
申请人： John Nigel Ellis , Paul Ronald Stribley , Jun Fu
发明人： John Nigel Ellis , Paul Ronald Stribley , Jun Fu
IPC分类号： H01L27/08
CPC分类号： H01L27/0629 , H01L21/823857 , H01L21/823878 , H01L21/823892 , H01L27/0922 , H01L29/7835
摘要： A CMOS circuit comprises at least one high voltage transistor (having gate and drain operating voltages of greater than 8V) and at least one high frequency capable transistor (having a maximum switching frequency of between 100 MHz and 1000 GHz) wherein said transistors are integrated on the same semiconductor substrate so as to allow the simple integration of high voltage circuits and RF (radio frequency) CMOS circuits on the same integrated circuit.
摘要翻译： CMOS电路包括至少一个高压晶体管（具有大于8V的栅极和漏极工作电压）和至少一个高频能力的晶体管（具有在100MHz和1000GHz之间的最大开关频率），其中所述晶体管集成在相同的半导体衬底，以便在同一集成电路上简单地集成高压电路和RF（射频）CMOS电路。

5. 发明授权

US08455955B2 Transistor array with shared body contact and method of manufacturing 有权
标题翻译：具有共享身体接触的晶体管阵列和制造方法
公开(公告)号：US08455955B2
公开(公告)日：2013-06-04
申请号：US12306947
申请日：2007-06-29
申请人： Paul Ronald Stribley , John Nigel Ellis
发明人： Paul Ronald Stribley , John Nigel Ellis
IPC分类号： H01L21/70
CPC分类号： H01L27/0203 , H01L21/823425 , H01L27/0705 , H01L27/0921 , H01L29/4238 , H01L29/78
摘要： An array of transistors arranged next to each other on a semiconductor material forming a substrate, the substrate comprising p-well or n-well diffusions forming a body, which diffusions are used as the body regions of the transistors, each transistor comprising a source, a drain and a gate, wherein the array of transistors further comprises at least one electrical connection to the body, wherein said electrical connection is shared by at least two transistors of said array. Also disclosed is a semiconductor device comprising at least one source, at least one drain, at least one gate between the at least one source and the at least one drain, and at least one structure of the same material as the at least one gate which does not have a connection means for electrical connection to the at least one gate.
摘要翻译：在形成衬底的半导体材料上彼此相邻布置的晶体管阵列，所述衬底包括形成体的p阱或n阱扩散，所述扩散用作晶体管的体区，每个晶体管包括源极，漏极和栅极，其中所述晶体管阵列还包括与所述主体的至少一个电连接，其中所述电连接由所述阵列的至少两个晶体管共享。还公开了一种半导体器件，其包括至少一个源极，至少一个漏极，至少一个源极与至少一个漏极之间的至少一个栅极，以及与该至少一个栅极相同的材料的至少一个结构，没有用于与至少一个门的电连接的连接装置。

6. 发明申请

US20130228868A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICES 有权
标题翻译：静电放电保护装置
公开(公告)号：US20130228868A1
公开(公告)日：2013-09-05
申请号：US13410016
申请日：2012-03-01
申请人： Paul Ronald Stribley
发明人： Paul Ronald Stribley
IPC分类号： H01L23/60 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/00 , H01L27/027 , H01L29/0626 , H01L29/0692 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/4238 , H01L29/7835 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion.
摘要翻译：一种用于静电放电（ESD）保护的半导体器件，包括源极，栅极，具有漏极扩散的漏极，以及从漏极扩散区延伸或位于其下方的扩散区域。源极，栅极，漏极和扩散区域位于衬底中或衬底上。扩散区域与漏极扩散器的栅极或外部边缘中的至少一个侧向间隔开。

7. 发明申请

US20100237465A1 CAPACITOR AND A METHOD OF MANUFACTURING A CAPACITOR 有权
标题翻译：电容器和制造电容器的方法
公开(公告)号：US20100237465A1
公开(公告)日：2010-09-23
申请号：US12669733
申请日：2008-07-18
申请人： Paul Ronald Stribley , Mark Parsons , Graham Chapman
发明人： Paul Ronald Stribley , Mark Parsons , Graham Chapman
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01G4/33 , H01L28/40
摘要： A device comprises a substrate (22); a first MiM capacitor (10,20,11) disposed over the substrate; and a second MiM capacitor (10′,20′,11) disposed over the first MiM capacitor. The first MiM capacitor and the second MiM capacitor are electrically connected in parallel. The two MiM capacitors are vertically stacked one above the other.Each MiM capacitor comprises an interconnection layer (10,10′) of the CMOS process as one plate and a thinner conductive layer (11,11′) as the second plate, with an insulating layer (20,20′) disposed therebetween. This allows each MiM capacitor to be formed between two CMOS process interconnection layers.The second plate of the second MiM capacitor is substantially co-extensive with the second plate of the first MiM capacitor, and is disposed substantially directly over the second plate of the first MiM capacitor. The same mask may be used to pattern the second plate of the second MiM capacitor and the second plate of the first MiM capacitor. This minimises the number of masks required, and so minimises the mask investment cost.
摘要翻译：一种器件包括衬底（22）; 设置在所述衬底上的第一MiM电容器（10,20,11）以及设置在所述第一MiM电容器上的第二MiM电容器（10'，20'，11）。第一个MiM电容器和第二个MiM电容器并联电连接。两个MiM电容器垂直堆叠在一起。每个MiM电容器包括作为一个板的CMOS工艺的互连层（10,10'）和作为第二板的较薄的导电层（11,11'），其间设置绝缘层（20,20'）。这允许在两个CMOS工艺互连层之间形成每个MiM电容器。第二MiM电容器的第二板与第一MiM电容器的第二板基本上共同扩展，并且基本上直接布置在第一MiM电容器的第二板上。可以使用相同的掩模来图案化第二MiM电容器的第二板和第一MiM电容器的第二板。这最大限度地减少了掩模所需的数量，从而最小化掩模投资成本。

8. 发明授权

US09331211B2 PN junctions and methods 有权
标题翻译： PN结和方法
公开(公告)号：US09331211B2
公开(公告)日：2016-05-03
申请号：US13393039
申请日：2009-08-28
申请人： Paul Ronald Stribley , Soon Tat Kong
发明人： Paul Ronald Stribley , Soon Tat Kong
IPC分类号： H01L29/49 , H01L29/866 , H01L23/525 , H01L29/06
CPC分类号： H01L29/866 , H01L23/5252 , H01L29/0688 , H01L2924/0002 , H01L2924/00
摘要： A PN junction includes first and second areas of silicon, wherein one of the first and second areas is n-type silicon and the other of the first and second areas is p-type silicon. The first area has one or more projections which at least partially overlap with the second area, so as to form at least one cross-over point, the cross-over point being a point at which an edge of the first area crosses over an edge of the second area.
摘要翻译： PN结包括第一和第二区域的硅，其中第一和第二区域之一是n型硅，而第一和第二区域中的另一个是p型硅。第一区域具有至少部分地与第二区域重叠的一个或多个突起，以便形成至少一个交叉点，所述交叉点是第一区域的边缘跨过边缘的点的第二个区域。

9. 发明授权

US06815264B2 Antifuses 有权
标题翻译：防潮
公开(公告)号：US06815264B2
公开(公告)日：2004-11-09
申请号：US10299133
申请日：2002-11-19
申请人： Paul Ronald Stribley , John N Ellis , Ian G Daniels
发明人： Paul Ronald Stribley , John N Ellis , Ian G Daniels
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method of producing an antifuse, comprises the steps of: depositing a layer of undoped or lightly doped polysilicon on a layer of silicon dioxide on a semiconductor wafer; doping one region of the polysilicon P+; doping another region of the polysilicon N+, leaving an undoped or lightly doped region between the P+ and N+ regions; and forming electrical connections to the P+ and N+ regions.

10. 发明申请

US20120211868A1 ULTRA-LOW VOLTAGE COEFFICIENT CAPACITORS 有权
标题翻译：超低电压系数电容器
公开(公告)号：US20120211868A1
公开(公告)日：2012-08-23
申请号：US13497078
申请日：2009-09-23
申请人： Paul Ronald Stribley , Soon Tat Kong , David John Verity
发明人： Paul Ronald Stribley , Soon Tat Kong , David John Verity
IPC分类号： H01L29/92
CPC分类号： H01L27/0207 , H01G4/08 , H01G4/20 , H01L27/0688 , H01L27/0805 , H01L28/40
摘要： A capacitor has first and second conducting plates and a dielectric region between the plates, wherein the dielectric region comprises two dielectric materials for each of which the variation of capacitance with voltage can be approximated by a polynomial having a linear coefficient and a quadratic coefficient, and wherein the quadratic coefficients of the two dielectric materials are of opposite sign. The capacitor comprises for example a first capacitor (42) and a second capacitor (44) that one connected in an anti-parallel manner. The insulating layer (18) of the first capacitor comprises silicon nitride and the insulating layer (16) of the second capacitor comprises silicon dioxide
摘要翻译：电容器具有第一导电板和第二导电板以及板之间的电介质区域，其中电介质区域包括两个电介质材料，每个电介质材料可以通过具有线性系数和二次系数的多项式近似电容与电压的变化，以及其中两个介电材料的二次系数具有相反的符号。电容器包括例如以反并联方式连接的第一电容器（42）和第二电容器（44）。第一电容器的绝缘层（18）包括氮化硅，第二电容器的绝缘层（16）包括二氧化硅

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