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    • 5. 发明授权
    • Reconfigurable high linearity low noise figure receiver requiring no interstage saw filter
    • 可重构的高线性度低噪声系数接收器,不需要级间锯式过滤器
    • US08433272B2
    • 2013-04-30
    • US12233420
    • 2008-09-18
    • Prasad S. GudemJose CabanillasLi-Chung ChangLi Liu
    • Prasad S. GudemJose CabanillasLi-Chung ChangLi Liu
    • H04K3/00H04B1/06H04B7/00
    • H04B1/109H03F1/3205H03F1/3211H03F3/193H03F3/245
    • A receiver includes a jammer detector configured to detect the presence or the absence of jamming in a communication signal within a gain state. The receiver further includes an amplifier configured to amplify the communication signal in a high linearity receiving mode or a low linearity receiving mode, wherein the high linearity receiving mode corresponds with a lower gain for the gain state in the amplifier relative to that of the low linearity receiving mode. In addition, the receiver includes a processing unit coupled to the jammer detector, the processing unit being configured to control the amplifier to amplify the communication signal in either the high linearity receiving mode or the low linearity receiving mode, based on the output of the jammer detector detecting the presence or the absence of jamming in the communication signal. A method is also provided for processing a communication signal in a receiver.
    • 接收机包括干扰检测器,其被配置为检测在增益状态内的通信信号中存在或不存在干扰。 接收器还包括放大器,被配置为以高线性度接收模式或低线性度接收模式放大通信信号,其中高线性度接收模式对应于放大器相对于低线性度的增益状态的较低增益 接收模式。 此外,接收机包括耦合到干扰检测器的处理单元,该处理单元被配置为基于干扰信号的输出来控制放大器以高线性接收模式或低线性度接收模式放大通信信号 检测器检测通信信号中是否存在干扰。 还提供了一种用于处理接收机中的通信信号的方法。
    • 7. 发明申请
    • DELTA-SIGMA MODULATOR CLOCK DITHERING IN A FRACTIONAL-N PHASE-LOCKED LOOP
    • DELTA-SIGMA调制器时钟在一个分段N相锁定环路
    • US20090212835A1
    • 2009-08-27
    • US12037503
    • 2008-02-26
    • Yang XuGang ZhangPrasad S. Gudem
    • Yang XuGang ZhangPrasad S. Gudem
    • H03L7/08
    • H03L7/1974
    • The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.
    • 在分数N锁相环中提供给Δ-Σ调制器的时钟信号被抖动。 在一个示例中,PLL包括新颖的可编程时钟抖动电路。 可编程时钟抖动电路可通过串行总线进行控制,以选择的几种方式对时钟信号的相位进行抖动。 如果时钟信号以第一种方式抖动(伪随机相位抖动),则由Δ-Σ调制器产生的数字噪声的功率在频带上扩展,从而降低噪声干扰其他电路的程度 。 如果时钟信号以第二种方式抖动(旋转相位抖动),则数字噪声的功率被频移,使得噪声干扰另一电路的程度降低。 可编程时钟抖动电路可以以其他方式进行控制。 例如,抖动可以可编程地禁用。
    • 8. 发明申请
    • ACTIVE CIRCUITS WITH LOAD LINEARIZATION
    • 具有负载线性化的有源电路
    • US20090051424A1
    • 2009-02-26
    • US11842712
    • 2007-08-21
    • Li LiuPrasad S. Gudem
    • Li LiuPrasad S. Gudem
    • H03F1/26H03F3/04H03F3/16
    • H04B1/109H03F1/223H03F1/3205H03F1/3211H03F3/45179H03F3/45188H03F2200/453H03F2203/45306H03F2203/45352H03F2203/45386H03F2203/45394H04B1/525
    • Active circuits with active loads linearized via distortion cancellation are described. In one design, an apparatus includes a first stage and a load stage. For an amplifier, the first stage amplifies an input signal and provides an output signal having a larger signal level. For a mixer, the first stage mixes an input signal with an LO signal and provides an output signal. The load stage provides an active load for the first stage and is linearized by canceling distortion generated by the active load. In one design, the load stage includes a first transistor that provides the active load and generates distortion due to its nonlinearity. The load stage further includes at least one transistor that generates a replica of the distortion from the first transistor. The distortion replica is used to cancel the distortion from the first transistor. The first stage may also be linearized with distortion cancellation.
    • 描述了通过失真消除线性化的有源负载的有源电路。 在一种设计中,装置包括第一级和负载级。 对于放大器,第一级放大输入信号并提供具有较大信号电平的输出信号。 对于混频器,第一级将输入信号与LO信号混频并提供输出信号。 负载级为第一级提供有效负载,并通过消除由有效负载产生的失真来线性化。 在一种设计中,负载级包括提供有源负载并由于其非线性而产生失真的第一晶体管。 负载级还包括至少一个晶体管,其产生来自第一晶体管的失真的复制品。 失真复制品用于消除第一晶体管的失真。 第一级也可以通过失真消除线性化。