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1. 发明授权

US11309026B2 Convolution operation method based on NOR flash array 有权
公开(公告)号：US11309026B2
公开(公告)日：2022-04-19
申请号：US16326946
申请日：2017-01-25
申请人： PEKING UNIVERSITY
发明人： Jinfeng Kang , Peng Huang , Runze Han , Xiaoyan Liu
IPC分类号： G11C16/04 , G11C16/10
摘要： The present disclosure relates to the field of semiconductor integrated circuits and manufacturing technologies thereof, and discloses a method and device for realizing a convolution operation based on an NOR flash storage structure. The NOR flash array has a structure of an array composed of a plurality of NOR flash cells. The convolution operation method includes: storing elements of a convolution kernel matrix into the NOR flash cells; converting elements of an input matrix into voltages and applying the voltages to gate terminals of the NOR flash cells; applying a driving voltage to source terminals of the NOR flash cells; and collecting, via drain terminals of the NOR flash cells, current values of each column to obtain a convolution operation result.

2. 发明申请

US20160313975A1 MULTI-BIT FULL ADDER BASED ON RESISTIVE-SWITCHING DEVICES AND OPERATION METHODS THEREOF 有权
标题翻译：基于电阻开关器件的多位全补充器及其操作方法
公开(公告)号：US20160313975A1
公开(公告)日：2016-10-27
申请号：US14897207
申请日：2013-12-31
申请人： PEKING UNIVERSITY
发明人： Lifeng Liu , Yi Hou , Bing Chen , Bin Gao , Dedong Han , Yi Wang , Xiaoyan Liu , Jinfeng Kang , Yuhua Cheng
IPC分类号： G06F7/501
CPC分类号： G06F7/5013 , G06F7/607
摘要： The present disclosure discloses a full adder based on resistive-switching devices and an operation method thereof. A multi-bit full adder circuit is constituted by using a cross-bar array of resistive-switching devices, wherein data of standard sums is stored on the principle diagonal of the cross-bar array in a nonvolatile manner, and carry data is stored in adjacent units on both sides of the principle diagonal. The carry data is stored according to whether the storage loop (crosstalk loop) is turned on. With the present disclosure, the multi-bit full adder circuit is significantly simplified. Thereby, additional circuits for generating a carry signal are reduced, the circuit delay and chip area are decreased, and the adder has an ability of nonvolatile storage.
摘要翻译：本公开公开了一种基于电阻式开关器件的全加器及其操作方法。通过使用电阻式开关器件的横杆阵列构成多位全加器电路，其中标准和的数据以非挥发性方式存储在交叉列阵列的原理对角线上，并且将数据存储在相邻单位两边的原则对角线。进位数据根据存储回路（串扰回路）是否开启而被存储。利用本公开，多位全加器电路被显着简化。因此，减少了用于产生进位信号的附加电路，电路延迟和芯片面积减小，并且加法器具有非易失性存储的能力。

3. 发明授权

US09111614B2 Resistive switching memory device and method for operating the same 有权
标题翻译：电阻式开关存储器件及其操作方法
公开(公告)号：US09111614B2
公开(公告)日：2015-08-18
申请号：US14367195
申请日：2012-12-21
申请人： PEKING UNIVERSITY
发明人： Jinfeng Kang , Bing Chen , Bin Gao , Feifei Zhang , Lifeng Liu , Xiaoyan Liu
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0028 , G11C13/003 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/74 , G11C2213/79
摘要： A resistive switching memory device and a method for operating the same are disclosed. The device includes a plurality of resistive switching memory units arranged in a matrix, each of which includes a switching element and a resistive switching device, and the switching element being connected to a word line at its control terminal, to the resistive switching device at one terminal, and to a bit line at the other terminal; a word line decoder adapted to decode an input address signal to switch on the switching element in at least one of resistive switching memory units; and a driving circuit adapted to apply a voltage pulse whose front edge changes slowly across the resistive switching device by the bit line synchronously with the switching-on of the switching element. Using the scheme of the above embodiments, the durability characteristic of the resistive switching device can be improved, such as degradation of high-low resistance value window and the failure of the device with transition times can be reduced.
摘要翻译：公开了一种电阻式开关存储器件及其操作方法。该装置包括以矩阵形式布置的多个电阻式开关存储器单元，每个电阻开关存储器单元包括开关元件和电阻开关器件，并且开关元件在其控制端连接到字线，一端连接到电阻开关器件终端，另一端的位线; 字线解码器，其适于对输入地址信号进行解码以接通至少一个电阻式开关存储器单元中的开关元件; 以及驱动电路，其适于施加电压脉冲，所述电压脉冲的前沿与所述开关元件的接通同步地通过所述位线缓慢跨越所述电阻开关器件。使用上述实施例的方案，可以改善电阻式开关装置的耐久性特性，例如高低电阻值窗口的劣化，并且可以减少具有转换时间的装置的故障。

4. 发明申请

US20140347913A1 RESISTIVE SWITCHING MEMORY DEVICE AND METHOD FOR OPERATING THE SAME 有权
标题翻译：电阻式开关存储器件及其操作方法
公开(公告)号：US20140347913A1
公开(公告)日：2014-11-27
申请号：US14367195
申请日：2012-12-21
申请人： PEKING UNIVERSITY
发明人： Jinfeng Kang , Bing Chen , Bin Gao , Feifei Zhang , Lifeng Liu , Xiaoyan Liu
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0028 , G11C13/003 , G11C13/0097 , G11C2013/0073 , G11C2013/0092 , G11C2213/74 , G11C2213/79
摘要： A resistive switching memory device and a method for operating the same are disclosed. The device includes a plurality of resistive switching memory units arranged in a matrix, each of which includes a switching element and a resistive switching device, and the switching element being connected to a word line at its control terminal, to the resistive switching device at one terminal, and to a bit line at the other terminal; a word line decoder adapted to decode an input address signal to switch on the switching element in at least one of resistive switching memory units; and a driving circuit adapted to apply a voltage pulse whose front edge changes slowly across the resistive switching device by the bit line synchronously with the switching-on of the switching element. Using the scheme of the above embodiments, the durability characteristic of the resistive switching device can be improved, such as degradation of high-low resistance value window and the failure of the device with transition times can be reduced.
摘要翻译：公开了一种电阻式开关存储器件及其操作方法。该装置包括以矩阵形式布置的多个电阻式开关存储器单元，每个电阻开关存储器单元包括开关元件和电阻开关器件，并且开关元件在其控制端连接到字线，一端连接到电阻开关器件终端，另一端的位线; 字线解码器，其适于对输入地址信号进行解码以接通至少一个电阻式开关存储器单元中的开关元件; 以及驱动电路，其适于施加电压脉冲，所述电压脉冲的前沿与所述开关元件的接通同步地通过所述位线缓慢跨越所述电阻开关器件。使用上述实施例的方案，可以改善电阻式开关装置的耐久性特性，例如高低电阻值窗口的劣化，并且可以减少具有转换时间的装置的故障。

5. 发明授权

US09196380B2 Method for measuring data retention characteristic of resistive random access memory device 有权
标题翻译：测量电阻随机存取存储器件数据保持特性的方法
公开(公告)号：US09196380B2
公开(公告)日：2015-11-24
申请号：US13705457
申请日：2012-12-05
申请人： Peking University
发明人： Lifeng Liu , Bin Gao , Jinfeng Kang , Xiaoyan Liu , Yi Wang
IPC分类号： G11C11/00 , G11C29/00 , G11C13/00 , G11C29/50 , G11C7/04 , G11C29/06
CPC分类号： G11C29/00 , G11C7/04 , G11C13/00 , G11C13/0007 , G11C13/0035 , G11C13/0069 , G11C29/06 , G11C29/50016 , G11C2013/0073
摘要： A method for measuring data retention characteristic of an RRAM device includes: a) controlling a temperature of a sample stage to maintain the RRAM device at a predetermined temperature; b) setting the RRAM device to a high-resistance state or a low-resistance state; c) measuring data retention time by applying a predetermined voltage to the RRAM device so that a resistive state failure of the RRAM device occurs; d) repeating the steps a)-c) to perform a plurality of measurements; e) calculating a resistive state failure probability F(t) of the RRAM device from the data retention time in the plurality of measurements; and f) fitting the resistive state failure probability F(t), and calculating predicted data retention time tE by using parameters obtained from the fitting. The data retention time of the RRAM device may be predicted by combining voltage acceleration and temperature acceleration.
摘要翻译：一种用于测量RRAM设备的数据保持特性的方法包括：a）控制样本台的温度以将RRAM设备维持在预定温度; b）将RRAM设备设置为高电阻状态或低电阻状态; c）通过向RRAM设备施加预定电压来测量数据保留时间，使得发生RRAM设备的电阻状态故障; d）重复步骤a）-c）以执行多个测量; e）从多个测量中的数据保留时间计算RRAM设备的电阻状态故障概率F（t）; f）拟合电阻状态故障概率F（t），并通过使用从拟合得到的参数来计算预测数据保持时间tE。可以通过组合电压加速度和温度加速度来预测RRAM设备的数据保留时间。

6. 发明授权

US08963275B2 Resistive-switching device capable of implementing multiary addition operation and method for multiary addition operation 有权
标题翻译：能够实现多重加法运算的电阻式开关装置及多次加法运算方法
公开(公告)号：US08963275B2
公开(公告)日：2015-02-24
申请号：US13706744
申请日：2012-12-06
申请人： Peking University
发明人： Jinfeng Kang , Bin Gao , Lifeng Liu , Xiaoyan Liu
IPC分类号： H01L27/24 , H01L45/00 , G11C17/06 , G11C13/00
CPC分类号： H01L27/2409 , G11C13/0007 , G11C13/003 , G11C17/06 , G11C2213/71 , G11C2213/72 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/122 , H01L45/1253 , H01L45/146 , H01L45/1683
摘要： A resistive-switching random access memory device includes a memory cell disposed between a bit line and a word line, the memory cell having a resistive-switching element (40) and a Schottky diode (30). The Schottky diode (30) and the resistive-switching element (40) are connected in series. The Schottky diode (30) includes a metal layer and a semiconductor layer contacting each other. An interface between the metal layer and the semiconductor layer has a non-planar shape.
摘要翻译：电阻切换随机存取存储器件包括位于位线和字线之间的存储单元，该存储单元具有电阻开关元件（40）和肖特基二极管（30）。肖特基二极管（30）和电阻开关元件（40）串联连接。肖特基二极管（30）包括金属层和彼此接触的半导体层。金属层和半导体层之间的界面具有非平面形状。

7. 发明申请

US20220321900A1 SYSTEM AND METHOD FOR COMPRESSING IMAGE BASED ON FLASH IN-MEMORY COMPUTING ARRAY 有权
公开(公告)号：US20220321900A1
公开(公告)日：2022-10-06
申请号：US17634442
申请日：2019-12-31
申请人： Peking University
发明人： Jinfeng Kang , Yachen Xiang , Peng Huang , Xiaoyan Liu , Runze Han
IPC分类号： H04N19/423 , H04N19/124 , H04N19/127
摘要： A system and a method for compressing an image based on a FLASH in-memory computing array are provided. The system includes: a convolutional neural network for encoding of the FLASH in-memory computing array, a convolutional neural network for decoding based on the FLASH in-memory computing array, and a quantization module; the convolutional neural network for encoding based on the FLASH in-memory computing array is configured to encode an original image to obtain a feature image; the quantization module is configured to quantize the feature image to obtain a quantized image; the convolutional neural network for decoding based on the FLASH in-memory computing array is configured to decode the quantized image to obtain a compressed image.

8. 发明授权

US11145365B2 Data search systems and methods 有权
公开(公告)号：US11145365B2
公开(公告)日：2021-10-12
申请号：US15778160
申请日：2016-12-20
申请人： PEKING UNIVERSITY
发明人： Jinfeng Kang , Peng Huang , Xiaoyan Liu , Lifeng Liu
IPC分类号： G11C5/14 , G11C13/00
摘要： The present disclosure provides a data search system and a data search method for determining whether there is stored information data matched with query information data in a storage circuit. The data search system comprises a storage circuit, a control circuit, and a feature extraction circuit, wherein the storage circuit comprises at least one storage unit which comprises a memristor crossbar array, a read/write unit, a decoder and a multiplexer, and the feature extraction circuit is configured to extract feature values of the query data. In the data search method, both the data matching process and the data storage process are performed in the memristor crossbar array under the control of the control circuit, which thus largely reduces the amount of data transmission while greatly improving the speed of data search using the characteristics of parallel calculation of the memristor crossbar array.

9. 发明授权

US09733900B2 Multi-bit full adder based on resistive-switching devices and operation methods thereof 有权
公开(公告)号：US09733900B2
公开(公告)日：2017-08-15
申请号：US14897207
申请日：2013-12-31
申请人： PEKING UNIVERSITY
发明人： Lifeng Liu , Yi Hou , Bing Chen , Bin Gao , Dedong Han , Yi Wang , Xiaoyan Liu , Jinfeng Kang , Yuhua Cheng
IPC分类号： G06F7/501 , G11C13/00 , G06F7/60
CPC分类号： G06F7/5013 , G06F7/607
摘要： The present disclosure discloses a full adder based on resistive-switching devices and an operation method thereof. A multi-bit full adder circuit is constituted by using a cross-bar array of resistive-switching devices, wherein data of standard sums is stored on the principle diagonal of the cross-bar array in a nonvolatile manner, and carry data is stored in adjacent units on both sides of the principle diagonal. The carry data is stored according to whether the storage loop (crosstalk loop) is turned on. With the present disclosure, the multi-bit full adder circuit is significantly simplified. Thereby, additional circuits for generating a carry signal are reduced, the circuit delay and chip area are decreased, and the adder has an ability of nonvolatile storage.

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