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1. 发明授权

US09225337B2 Temperature threshold circuit with hysteresis 有权
标题翻译：具有迟滞的温度阈值电路
公开(公告)号：US09225337B2
公开(公告)日：2015-12-29
申请号：US14191684
申请日：2014-02-27
申请人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
发明人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
IPC分类号： G01K1/02 , H03K21/10 , G01K7/00 , H03K21/38 , G01K13/00
CPC分类号： H03K21/10 , G01K1/028 , G01K3/005 , G01K7/32 , G01K13/002 , H03K21/38
摘要： A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication.
摘要翻译：一种用于确定相对于阈值温度的温度阈值指示的电路。电路包括定时器电路和具有计数器的温度传感器电路，其计数器的输出与温度有关。在由定时器电路确定的周期结束时，比较器电路将计数器的计数与阈值温度的指示进行比较，以确定阈值指示的状态。响应于阈值指示的状态改变，电路将计数时间或计数器输出与温度的关系改变，以提供阈值指示的滞后。

2. 发明授权

US09672938B2 Memory with redundancy 有权
公开(公告)号：US09672938B2
公开(公告)日：2017-06-06
申请号：US14258730
申请日：2014-04-22
申请人： George P. Hoekstra , Perry H. Pelley , Ravindraraj Ramaraju
发明人： George P. Hoekstra , Perry H. Pelley , Ravindraraj Ramaraju
IPC分类号： G11C7/00 , G11C29/44 , G11C29/00 , G11C29/12
CPC分类号： G11C29/44 , G11C29/12 , G11C29/83
摘要： Structures for substituting single bits in an array may include a first array having a plurality of word lines, and for each of the plurality of word lines a memory operable to store a bit substitution column value, and a first data output line operable to communicate the bit substitution column value to a write data shifter. The bit substitution column value may be associated with a bit substitution column in a second array, and the write data shifter may be operable to substitute the bit by shifting data to a redundancy column in the first array.

3. 发明申请

US20150244375A1 TEMPERATURE THRESHOLD CIRCUIT WITH HYSTERESIS 有权
标题翻译：具有迟滞的温度阈值电路
公开(公告)号：US20150244375A1
公开(公告)日：2015-08-27
申请号：US14191684
申请日：2014-02-27
申请人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
发明人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
IPC分类号： H03K21/10 , G01K7/00
CPC分类号： H03K21/10 , G01K1/028 , G01K3/005 , G01K7/32 , G01K13/002 , H03K21/38
摘要： A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication.
摘要翻译：一种用于确定相对于阈值温度的温度阈值指示的电路。电路包括定时器电路和具有计数器的温度传感器电路，其计数器的输出与温度有关。在由定时器电路确定的周期结束时，比较器电路将计数器的计数与阈值温度的指示进行比较，以确定阈值指示的状态。响应于阈值指示的状态改变，电路将计数时间或计数器输出与温度的关系改变，以提供阈值指示的滞后。

4. 发明申请

US20140269131A1 MEMORY WITH POWER SAVINGS FOR UNNECESSARY READS 有权
标题翻译：具有省电功能的记忆用于不必要的阅读
公开(公告)号：US20140269131A1
公开(公告)日：2014-09-18
申请号：US13826427
申请日：2013-03-14
申请人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
IPC分类号： G11C7/08
CPC分类号： G11C7/08 , G11C8/12
摘要： A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
摘要翻译：存储器件包括多个读出放大器，包括存储器单元的第一子集的存储器单元阵列和多个字线。每个字线被耦合到存储器单元的相应行中的每个存储器单元，并且每行存储器单元包括存储器单元的第一子集的一个存储单元。多个控制字线中的每一个耦合到存储器单元的第一子集中的相应的一个存储器单元，并且存储器单元的第一子集中的每个存储单元产生一个读出放大器控制信号，相应的多个读出放大器之一。

5. 发明授权

US07564738B2 Double-rate memory 有权
标题翻译：双速率内存
公开(公告)号：US07564738B2
公开(公告)日：2009-07-21
申请号：US11464129
申请日：2006-08-11
申请人： Perry H. Pelley, III , George P. Hoekstra
发明人： Perry H. Pelley, III , George P. Hoekstra
IPC分类号： G11C8/16
CPC分类号： G11C8/10 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C8/18
摘要： A double-rate memory has an array of single word line memory cells arranged in rows and columns. The single word line memory cells provide and store data via a first port. Addressing and control circuitry is coupled to the array of single word line memory cells. The addressing and control circuitry receives an address enable signal to initiate an access of the array whereby an address is received, decoded, and corresponding data retrieved or stored. Edge detection circuitry receives a memory clock and provides the address enable signal upon each rising edge and each falling edge of the memory clock to perform two memory operations in a single cycle of the memory clock. A memory operation includes addressing the memory and storing data in the memory or retrieving and latching data from the memory. In another form a double-rate dual port memory permits two independent read/write memory accesses in a single memory cycle.
摘要翻译：双速率存储器具有以行和列排列的单个字线存储单元阵列。单个字线存储单元通过第一端口提供和存储数据。寻址和控制电路耦合到单个字线存储单元的阵列。寻址和控制电路接收地址使能信号以启动阵列的访问，由此接收，解码地址并检索或存储对应的数据。边缘检测电路接收存储器时钟，并在存储器时钟的每个上升沿和每个下降沿提供地址使能信号，以在存储器时钟的单个周期中执行两个存储器操作。存储器操作包括寻址存储器并将数据存储在存储器中或从存储器检索和锁存数据。在另一种形式中，双速率双端口存储器允许在单个存储器周期中进行两个独立的读/写存储器存取。

6. 发明授权

US06608789B2 Hysteresis reduced sense amplifier and method of operation 有权
标题翻译：滞后减小的感测放大器和操作方法
公开(公告)号：US06608789B2
公开(公告)日：2003-08-19
申请号：US10027547
申请日：2001-12-21
申请人： Steven C. Sullivan , Perry H. Pelley , George P. Hoekstra
发明人： Steven C. Sullivan , Perry H. Pelley , George P. Hoekstra
IPC分类号： G11C700
CPC分类号： G11C7/065
摘要： A sense amplifier (40) uses a body shorting device (60) to selectively electrically short circuit the bodies of two transistors (44, 48) that function as a differential sensing pair. Equalization of charge injected into the bodies functions to minimize offset voltage between the two bodies. The body shorting device selectively shorts the bodies in response to a body control signal after a sense operation and after asserting a precharging signal to initiate precharging of the sense amplifier's outputs.
摘要翻译：读出放大器（40）使用主体短路装置（60）来选择性地使作为差分感测对的两个晶体管（44,48）的主体电短路。注入到体内的电荷的均衡起到使两个物体之间的失调电压最小化的作用。身体短路装置在感测操作之后并且在确定预充电信号以启动感测放大器的输出的预充电之后，响应于身体控制信号选择性地短路身体。

7. 发明授权

US4802129A RAM with dual precharge circuit and write recovery circuitry 失效
标题翻译： RAM具有双预充电电路和写恢复电路
公开(公告)号：US4802129A
公开(公告)日：1989-01-31
申请号：US128559
申请日：1987-12-03
申请人： George P. Hoekstra , Perry H. Pelley, III
发明人： George P. Hoekstra , Perry H. Pelley, III
IPC分类号： G11C7/10 , G11C7/22 , G11C11/419 , G11C7/00 , G11C8/00
CPC分类号： G11C11/419 , G11C7/10 , G11C7/22
摘要： A memory is written via data lines which are driven by a write driver. The data lines are coupled to a selected bit line pair as determined by a column address. The data lines are driven to a logic state representative of a data input signal by a write driver. The write driver is enabled during the presence of a write enable pulse. The write enable pulse is generated in response to a read mode to write mode transition and also in response to a transition of the data input signal. The data lines are precharged in response to a transition of the data input signal that occurs during the write mode.
摘要翻译：通过由写入驱动器驱动的数据线写入存储器。数据线被耦合到由列地址确定的所选位线对。数据线由写入驱动器驱动到代表数据输入信号的逻辑状态。在存在写使能脉冲时，写驱动器被使能。写使能脉冲响应于写模式转换的读模式并且还响应于数据输入信号的转换而被产生。响应于在写入模式期间发生的数据输入信号的转变，数据线被预充电。

8. 发明授权

US09317087B2 Memory column drowsy control 有权
标题翻译：内存列困倦控制
公开(公告)号：US09317087B2
公开(公告)日：2016-04-19
申请号：US13689331
申请日：2012-11-29
申请人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
摘要翻译：根据至少一个实施例，提供列级功率控制粒度以使用昏迷列控制位来控制存储器的低功率状态，以控制单个列级的低功率状态，以保护存储器免于弱位故障。根据至少一个实施例，提供了在存储器阵列中使用专用行位单元的方法，其中行中的每个位控制阵列中相应列的低功率状态。使用特殊的控制信号来访问字线，字线在常规字线地址空间之外。提供了一种机制来指定弱位列，并设置与该特定列相对应的控制位以禁用该列的困倦/低功率状态。

9. 发明授权

US09117498B2 Memory with power savings for unnecessary reads 有权
标题翻译：记忆功能，节省了不必要的读数
公开(公告)号：US09117498B2
公开(公告)日：2015-08-25
申请号：US13826427
申请日：2013-03-14
申请人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
IPC分类号： G11C7/08 , G11C8/12
CPC分类号： G11C7/08 , G11C8/12
摘要： A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
摘要翻译：存储器件包括多个读出放大器，包括存储器单元的第一子集的存储器单元阵列和多个字线。每个字线被耦合到存储器单元的相应行中的每个存储器单元，并且每行存储器单元包括存储器单元的第一子集的一个存储单元。多个控制字线中的每一个耦合到存储器单元的第一子集中的相应的一个存储器单元，并且存储器单元的第一子集中的每个存储单元产生一个读出放大器控制信号，相应的多个读出放大器之一。

10. 发明授权

US06928005B2 Domino comparator capable for use in a memory array 有权
公开(公告)号：US06928005B2
公开(公告)日：2005-08-09
申请号：US10703657
申请日：2003-11-05
申请人： Ravindraraj Ramaraju , George P. Hoekstra
发明人： Ravindraraj Ramaraju , George P. Hoekstra
IPC分类号： G11C7/00 , G11C11/00 , G11C15/00
CPC分类号： G11C15/00
摘要： A memory including a NOR logic gate having an input coupled to a bitline (BL) and an input to receive the complement of the data value (DATABAR). The memory also including a NOR logic gate having an input coupled to the bitline bar (BLBAR) and an input to receive the data value (DATA). A combine stage is also included having an input coupled to an output of the NOR logic gate, an input coupled to an output of the NOR logic gate, and an output to provide a miss indicator (MISS). The miss indicator (MISS) indicates when a value on the bitline (BL) does not match the data value (DATA). The memory also comprising a plurality of bitcells coupled to the bitline (BL) and bitline bar (BLBAR), where each of the plurality of bitcells is coupled to a corresponding word line.

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