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1. 发明授权

US08441266B1 Sensing circuit 有权
标题翻译：感应电路
公开(公告)号：US08441266B1
公开(公告)日：2013-05-14
申请号：US12537609
申请日：2009-08-07
申请人： Ping Xiao , Weiying Ding
发明人： Ping Xiao , Weiying Ding
IPC分类号： H01H85/30 , G01R31/02 , G08B21/00
CPC分类号： G01R31/07 , G11C7/062 , G11C17/16 , G11C17/18 , G11C29/027 , G11C29/50008
摘要： A sensing circuit for comparing current flow through a reference resistance with current flow through a resistive device under test (DUT) such as a fuse. The sensing circuit includes a comparator having a first PMOS transistor and a first NMOS transistor connected in series between a first input and a first node and a second PMOS transistor and a second NMOS transistor connected in series between a second input and the first node. The first PMOS and NMOS transistors are cross-coupled with the second PMOS and NMOS transistors. Specifically, a first output is connected to the first node to the gates of the second PMOS and second NMOS transistors and a second output is connected to the second node and to the gates of the first PMOS and first NMOS transistors. The reference resistance is connected to one of the inputs and the DUT is connected to the other input.
摘要翻译：用于将通过参考电阻的电流与通过被测电阻器件（DUT）（例如保险丝）的电流进行比较的感测电路。感测电路包括具有第一PMOS晶体管和第一NMOS晶体管的比较器，第一PMOS晶体管和第一NMOS晶体管串联连接在第一输入和第一节点之间，第二PMOS晶体管和第二NMOS晶体管串联连接在第二输入端和第一节点之间。第一PMOS和NMOS晶体管与第二PMOS和NMOS晶体管交叉耦合。具体地说，第一输出端连接到第一PMOS晶体管和第二NMOS晶体管的栅极，第二输出端连接到第二节点和第一PMOS和第一NMOS晶体管的栅极。参考电阻连接到其中一个输入，DUT连接到另一个输入。

2. 发明授权

US09086434B1 Methods and systems for voltage reference power detection 有权
标题翻译：电压参考功率检测的方法和系统
公开(公告)号：US09086434B1
公开(公告)日：2015-07-21
申请号：US13312571
申请日：2011-12-06
申请人： Ping Xiao , Weiying Ding
发明人： Ping Xiao , Weiying Ding
IPC分类号： G01R19/00
CPC分类号： G01R19/0092 , G01R31/40
摘要： Methods and systems for detection and monitoring of power supply voltage and voltage reference circuitry are provided. In one embodiment of the invention, a first signal is set to be proportional to a power supply voltage in response to a determination from control circuitry that an output voltage of bandgap voltage reference circuitry is less than a first threshold voltage. The first signal is set to a logic low level in response to a determination from control circuitry that the output voltage of the bandgap voltage reference circuit is greater than the first threshold voltage, wherein the first threshold voltage is less than a bandgap reference voltage. A value of a reset signal is determined based at least in part on the first signal.
摘要翻译：提供了用于检测和监测电源电压和电压参考电路的方法和系统。在本发明的一个实施例中，响应于来自控制电路的确定，带隙电压参考电路的输出电压小于第一阈值电压，将第一信号设置为与电源电压成比例。响应于来自控制电路的确定，第一信号被设置为逻辑低电平，即带隙电压参考电路的输出电压大于第一阈值电压，其中第一阈值电压小于带隙参考电压。至少部分地基于第一信号来确定复位信号的值。

3. 发明授权

US07675440B1 Thermometer-code-to-binary encoders 失效
标题翻译：温度计代码到二进制编码器
公开(公告)号：US07675440B1
公开(公告)日：2010-03-09
申请号：US12111146
申请日：2008-04-28
申请人： Ping Xiao , William W. Bereza , Weiying Ding , Mohsen Moussavi
发明人： Ping Xiao , William W. Bereza , Weiying Ding , Mohsen Moussavi
IPC分类号： H03M1/06
CPC分类号： H03M1/0809 , H03M7/165
摘要： An encoder is provided for converting thermometer code data with bubbles to binary format. An integrated circuit may have circuitry such as digital phase-locked loop circuitry. A thermometer code data word may be used as a control signal for the circuitry. It may be desirable to monitor the thermometer code data word for testing or for downstream processing by control logic on the integrated circuit. The encoder performs thermometer code to binary encoding without requiring that the thermometer code be error corrected to remove bubbles. A bubble detection circuit may be used to detect when the thermometer code data contains bubbles. The encoder may use carry look-ahead adders and pipeline stages.
摘要翻译：提供了一种用于将温度计代码数据与气泡转换为二进制格式的编码器。集成电路可以具有诸如数字锁相环电路的电路。温度计代码数据字可以用作电路的控制信号。可能希望通过集成电路上的控制逻辑来监测温度计代码数据字进行测试或下游处理。编码器将温度计代码执行二进制编码，而不需要对温度计代码进行纠错以消除气泡。可以使用气泡检测电路来检测温度计代码数据何时包含气泡。编码器可以使用前置加法器和流水线级。

4. 发明授权

US09083365B1 Thermometer-code-to-binary encoders 有权
标题翻译：温度计代码到二进制编码器
公开(公告)号：US09083365B1
公开(公告)日：2015-07-14
申请号：US12696027
申请日：2010-01-28
申请人： Ping Xiao , William W. Bereza , Weiying Ding , Mohsen Moussavi
发明人： Ping Xiao , William W. Bereza , Weiying Ding , Mohsen Moussavi
IPC分类号： H03M1/06 , H03M7/16 , H03M1/08
CPC分类号： H03M1/0809 , H03M7/165
摘要： An encoder is provided for converting thermometer code data with bubbles to binary format. An integrated circuit may have circuitry such as digital phase-locked loop circuitry. A thermometer code data word may be used as a control signal for the circuitry. It may be desirable to monitor the thermometer code data word for testing or for downstream processing by control logic on the integrated circuit. The encoder performs thermometer code to binary encoding without requiring that the thermometer code be error corrected to remove bubbles. A bubble detection circuit may be used to detect when the thermometer code data contains bubbles. The encoder may use carry look-ahead adders and pipeline stages.
摘要翻译：提供了一种用于将温度计代码数据与气泡转换为二进制格式的编码器。集成电路可以具有诸如数字锁相环电路的电路。温度计代码数据字可以用作电路的控制信号。可能希望通过集成电路上的控制逻辑来监测温度计代码数据字进行测试或下游处理。编码器将温度计代码执行二进制编码，而不需要对温度计代码进行纠错以消除气泡。可以使用气泡检测电路来检测温度计代码数据何时包含气泡。编码器可以使用前置加法器和流水线级。

5. 发明授权

US08405535B1 Integrated circuit with configurable analog to digital converter 有权
标题翻译：集成电路与可配置的模数转换器
公开(公告)号：US08405535B1
公开(公告)日：2013-03-26
申请号：US13205512
申请日：2011-08-08
申请人： Ping Xiao , Weiying Ding
发明人： Ping Xiao , Weiying Ding
IPC分类号： H03M3/00
CPC分类号： H03M3/394 , H03M3/398 , H03M3/43 , H03M3/45 , H03M3/452 , H03M3/454 , H03M3/456
摘要： Circuits, methods, and systems for implementing an Analog to Digital Converter (ADC) in an Integrated Circuit (IC) are provided. An IC includes an analog modulator, a digital filter coupled to the analog modulator, and a decimator coupled to the digital filter. The analog modulator includes one or more discrete integrators and a feedback path. A first discrete integrator from the one or more discrete integrators is operable to receive an analog input of the ADC. The feedback path couples an output of the analog modulator to at least one of the one or more discrete integrators. Further, the decimator is operable to produce the output of the ADC, and the IC is operable to receive an IC configuration file that specifies how the discrete integrators are connected in the analog modulator, parameters of the digital filter, and parameters of the decimator.
摘要翻译：提供了在集成电路（IC）中实现模数转换器（ADC）的电路，方法和系统。 IC包括模拟调制器，耦合到模拟调制器的数字滤波器和耦合到数字滤波器的抽取器。模拟调制器包括一个或多个离散积分器和反馈路径。来自一个或多个离散积分器的第一个离散积分器可操作以接收ADC的模拟输入。反馈路径将模拟调制器的输出耦合到一个或多个离散积分器中的至少一个。此外，抽取器可操作以产生ADC的输出，并且IC可操作以接收指定模拟调制器中的离散积分器如何连接的IC配置文件，数字滤波器的参数以及抽取器的参数。

6. 发明授权

US08154942B1 Integrated circuits with fuse programming and sensing circuitry 有权
标题翻译：具有保险丝编程和感应电路的集成电路
公开(公告)号：US08154942B1
公开(公告)日：2012-04-10
申请号：US12272727
申请日：2008-11-17
申请人： Ping Xiao , Weiying Ding , Myron Wai Wong , Mario E. Guzman
发明人： Ping Xiao , Weiying Ding , Myron Wai Wong , Mario E. Guzman
IPC分类号： G11C5/14
CPC分类号： G11C17/18
摘要： Circuitry on an integrated circuit is provided that may be used to program fuses such as polysilicon fuses. Fuse programming may be performed using an elevated power supply voltage. Other circuitry on the integrated circuit may be powered using a standard power supply voltage that is less than the elevated power supply voltage. Fuse sensing may be performed using the standard power supply voltage. A control block may be used to produce a fuse programming control signal. Power-on-reset circuitry may monitor the elevated power supply voltage and may produce a corresponding elevated power supply voltage power-on-reset signal indicative of whether the elevated power supply voltage is valid. The power-on-reset circuitry may also produce a standard power supply power-on-reset signal indicative of whether the standard power supply voltage is valid. The power-on-reset signals may be used in controlling fuse programming and fuse sensing.
摘要翻译：提供集成电路中的电路，其可用于编程诸如多晶硅熔丝的保险丝。可以使用升高的电源电压来执行保险丝编程。集成电路中的其他电路可以使用小于升高的电源电压的标准电源电压供电。可以使用标准电源电压进行保险丝感测。可以使用控制块来产生保险丝编程控制信号。上电复位电路可以监视升高的电源电压，并且可以产生指示升高的电源电压是否有效的相应的升高的电源电压上电复位信号。上电复位电路还可以产生指示标准电源电压是否有效的标准电源上电复位信号。上电复位信号可用于控制熔丝编程和熔丝感测。

7. 发明授权

US07639052B2 Power-on-reset circuitry 失效
标题翻译：上电复位电路
公开(公告)号：US07639052B2
公开(公告)日：2009-12-29
申请号：US11784373
申请日：2007-04-06
申请人： Ping Xiao , Weiying Ding , Leo Min Maung
发明人： Ping Xiao , Weiying Ding , Leo Min Maung
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F1/24 , H03K17/22 , H03K17/30 , H03K19/17736 , H03K19/17764
摘要： Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals. Brownout detection blocking circuitry may be provided to prevent the output from one of the trip point detectors from influencing the power-on-reset circuitry.
摘要翻译：为诸如可编程逻辑器件集成电路的集成电路提供上电复位电路。上电复位电路可以使用基于比较器的跳变点电压检测器来监视电源电压。跳变点检测器可以使用电路从带隙参考电压产生跳变点电压。控制器逻辑可以处理来自跳变点检测器的信号以产生相应的上电复位信号。上电复位电路可以包含抑制电源电压尖峰噪声的噪声滤波器。在测试期间可能会阻止上电复位电路的正常工作。当带隙参考电压尚未达到所需的电平时，上电复位电路可能会被禁止。上电复位电路可能对电源信号使用的上电顺序敏感或不敏感。可以提供掉电检测阻塞电路以防止一个跳变点检测器的输出影响上电复位电路。

8. 发明申请

US20080246509A1 Power-on-reset circuitry 失效
标题翻译：上电复位电路
公开(公告)号：US20080246509A1
公开(公告)日：2008-10-09
申请号：US11784373
申请日：2007-04-06
申请人： Ping Xiao , Weiying Ding , Leo Min Maung
发明人： Ping Xiao , Weiying Ding , Leo Min Maung
IPC分类号： H03K19/177 , H03L7/00
CPC分类号： H03L7/00 , G06F1/24 , H03K17/22 , H03K17/30 , H03K19/17736 , H03K19/17764
摘要： Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals. Brownout detection blocking circuitry may be provided to prevent the output from one of the trip point detectors from influencing the power-on-reset circuitry.
摘要翻译：为诸如可编程逻辑器件集成电路的集成电路提供上电复位电路。上电复位电路可以使用基于比较器的跳变点电压检测器来监视电源电压。跳变点检测器可以使用电路从带隙参考电压产生跳变点电压。控制器逻辑可以处理来自跳变点检测器的信号以产生相应的上电复位信号。上电复位电路可以包含抑制电源电压尖峰噪声的噪声滤波器。在测试期间可能会阻止上电复位电路的正常工作。当带隙参考电压尚未达到所需的电平时，上电复位电路可能会被禁止。上电复位电路可能对电源信号使用的上电顺序敏感或不敏感。可以提供掉电检测阻塞电路以防止一个跳变点检测器的输出影响上电复位电路。

9. 发明授权

US07058880B1 Techniques for programming and verifying data in a programmable circuit 失效
标题翻译：用于在可编程电路中编程和验证数据的技术
公开(公告)号：US07058880B1
公开(公告)日：2006-06-06
申请号：US10032832
申请日：2001-12-26
申请人： Weiying Ding , Brad Vest
发明人： Weiying Ding , Brad Vest
IPC分类号： H06F11/00 , G11B5/09
CPC分类号： G11C16/3454 , G11C16/3459
摘要： The present invention includes techniques for programming and verifying data in a programmable circuit. Programmable circuits such as PLDs may include a plurality of rows and columns of memory cells. Data is programmed into memory elements associated with the rows and columns. Subsequently, the programmed data may be extracted for verification. A first word line may be selected by first word line address bits in row shift registers. Data programmed into the first word line is loaded into column shift registers for verification during one or more verify steps. During a program step, data is programmed into memory elements in a second word line that is selected by the first word line address bits. The present invention also provides a technique for shifting program data bits into the column shift registers at the same time that verify data bits are shifted out of the column shift registers.
摘要翻译：本发明包括用于编程和验证可编程电路中的数据的技术。 PLD等可编程电路可以包括存储单元的多个行和列。数据被编程到与行和列相关联的存储器元件中。随后，可以提取编程数据以进行验证。第一字线可以由行移位寄存器中的第一字线地址位选择。编入第一个字线的数据被加载到列移位寄存器中，以在一个或多个验证步骤中进行验证。在程序步骤期间，数据被编程到由第一字线地址位选择的第二字线中的存储器元件中。本发明还提供了一种用于在将校验数据位移出列移位寄存器的同时将程序数据位移位到列移位寄存器中的技术。

10. 发明授权

US06965251B1 Input buffer with hysteresis option 失效
标题翻译：具有滞后选项的输入缓冲器
公开(公告)号：US06965251B1
公开(公告)日：2005-11-15
申请号：US10708243
申请日：2004-02-18
申请人： Neil Nghia Tran , Nima Gilanpour , Myron W. Wong , Weiying Ding
发明人： Neil Nghia Tran , Nima Gilanpour , Myron W. Wong , Weiying Ding
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/018585
摘要： The invention provides a high-speed buffer that may used at the input of an integrated circuit, such as an input buffer. This buffer may be configured for use as a standard buffer with a single switching threshold, such as a TTL-to-CMOS buffer, or used as a Schmitt trigger with hysteresis, which as at least two switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.
摘要翻译：本发明提供了可以在诸如输入缓冲器的集成电路的输入端使用的高速缓冲器。该缓冲器可以被配置为用作具有单个切换阈值的标准缓冲器，例如TTL至CMOS缓冲器，或者用作具有迟滞的施密特触发器，其作为至少两个切换阈值。集成电路可以是可编程逻辑器件（PLD）或现场可编程门阵列（FPGA），但是在其他实施例中，集成电路可以是其他类型的器件，例如微处理器，ASIC或存储器。

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