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1. 发明授权

US09173282B2 Interconnect structures and methods of making the same 有权
标题翻译：互连结构和制作方法
公开(公告)号：US09173282B2
公开(公告)日：2015-10-27
申请号：US13638536
申请日：2011-03-31
申请人： Pulugurtha Markondeya Raj , Nitesh Kumbhat , Venkatesh Sundaram , Rao R. Tummala
发明人： Pulugurtha Markondeya Raj , Nitesh Kumbhat , Venkatesh Sundaram , Rao R. Tummala
IPC分类号： H01R9/00 , H05K1/02 , H01L23/498 , H01L25/065 , H01R12/52 , H01R12/71 , H05K3/34 , H05K1/18 , H05K3/10 , H01L29/41 , H01L23/13 , H01L25/10 , H01L23/00
CPC分类号： H05K1/0213 , H01L23/13 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L29/413 , H01L2224/131 , H01L2224/16237 , H01L2224/45147 , H01L2224/81191 , H01L2224/81203 , H01L2224/81207 , H01L2224/81385 , H01L2224/81399 , H01L2224/81815 , H01L2224/8182 , H01L2224/8185 , H01L2224/81897 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/00014 , H01L2924/01029 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/1579 , H01L2924/15791 , H01R12/52 , H01R12/714 , H05K1/18 , H05K3/107 , H05K3/3436 , H05K2201/0248 , H05K2201/0281 , H05K2201/10378 , H05K2201/10674 , Y02P70/613 , H01L2924/014 , H01L2924/00 , H01L2224/48
摘要： The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.
摘要翻译：本发明的各种实施例提供了一种应力消除的二级互连结构，其低成本并且适应低TCE封装和PCB之间的TCE不匹配。互连结构的各种实施例是可再加工的，并且可以缩放到约1毫米（mm）至约150微米（μm）的间距。互连结构包括介电体元件和提供两个电子部件之间的导电路径的至少一个互连阵列。每个互连阵列包括提供导电性和整体互连结构的柔性的多条导线。本发明的互连结构的多功能性和可扩展性使其成为在目前的二维和不断发展的三维IC结构中使用的理想结构。

2. 发明申请

US20130107485A1 INTERCONNECT STRUCTURES AND METHODS OF MAKING THE SAME 有权
标题翻译：互连结构及其制作方法
公开(公告)号：US20130107485A1
公开(公告)日：2013-05-02
申请号：US13638536
申请日：2011-03-31
申请人： Pulugurtha Markondeya Raj , Nitesh Kumbhat , Venkatesh Sundaram , Rao R. Tummala
发明人： Pulugurtha Markondeya Raj , Nitesh Kumbhat , Venkatesh Sundaram , Rao R. Tummala
IPC分类号： H05K1/02 , H05K3/10 , H05K1/18
CPC分类号： H05K1/0213 , H01L23/13 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L29/413 , H01L2224/131 , H01L2224/16237 , H01L2224/45147 , H01L2224/81191 , H01L2224/81203 , H01L2224/81207 , H01L2224/81385 , H01L2224/81399 , H01L2224/81815 , H01L2224/8182 , H01L2224/8185 , H01L2224/81897 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/00014 , H01L2924/01029 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/1579 , H01L2924/15791 , H01R12/52 , H01R12/714 , H05K1/18 , H05K3/107 , H05K3/3436 , H05K2201/0248 , H05K2201/0281 , H05K2201/10378 , H05K2201/10674 , Y02P70/613 , H01L2924/014 , H01L2924/00 , H01L2224/48
摘要： The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.
摘要翻译：本发明的各种实施例提供了一种应力消除的二级互连结构，其低成本并且适应低TCE封装和PCB之间的TCE不匹配。互连结构的各种实施例是可再加工的，并且可以缩放到约1毫米（mm）至约150微米（母体）的间距。互连结构包括介电体元件和提供两个电子部件之间的导电路径的至少一个互连阵列。每个互连阵列包括提供导电性和整体互连结构的柔性的多条导线。本发明的互连结构的多功能性和可扩展性使其成为在目前的二维和不断发展的三维IC结构中使用的理想结构。

3. 发明申请

US20130270695A1 Second Level Interconnect Structures and Methods of Making the Same 有权
标题翻译：二级互连结构及其制作方法
公开(公告)号：US20130270695A1
公开(公告)日：2013-10-17
申请号：US13825815
申请日：2011-09-20
申请人： Pulugurtha Markondeya Raj , Nitesh Kumbhat , Venky Sundaraman , Rao R. Tummala , Xian Qin
发明人： Pulugurtha Markondeya Raj , Nitesh Kumbhat , Venky Sundaraman , Rao R. Tummala , Xian Qin
IPC分类号： H01L23/00
CPC分类号： H01L24/16 , H01L24/11 , H01L2224/16225 , H01L2924/14 , H01L2924/181 , H05K1/0271 , H05K3/3436 , H05K3/4007 , Y02P70/613 , H01L2924/00012 , H01L2924/00
摘要： The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, therefore enhancing compliance between the two electronic components. The versatility, scalability, and stress-relieving properties of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.
摘要翻译：本发明的各种实施例提供了一种应力消除的二级互连结构，其低成本并且适应低TCE封装和PCB之间的TCE不匹配。互连结构的各种实施例是可再加工的，并且可以缩放到约1毫米（mm）至约150微米（母体）的间距。所述互连结构至少包括第一焊盘，支撑柱和焊料凸块，其中所述第一焊盘和支撑柱可操作以吸收基本上所有的塑性应变，从而提高所述两个电子部件之间的顺应性。本发明的互连结构的多功能性，可扩展性和应力消除特性使其成为在目前的二维和不断发展的三维IC结构中使用的理想结构。

4. 发明授权

US08970036B2 Stress relieving second level interconnect structures and methods of making the same 有权
标题翻译：应力消除二级互连结构及其制作方法
公开(公告)号：US08970036B2
公开(公告)日：2015-03-03
申请号：US13825815
申请日：2011-09-20
申请人： Pulugurtha Markondeya Raj , Nitesh Kumbhat , Venkatesh V. Sundaram , Rao R. Tummala , Xian Qin
发明人： Pulugurtha Markondeya Raj , Nitesh Kumbhat , Venkatesh V. Sundaram , Rao R. Tummala , Xian Qin
IPC分类号： H01L23/48 , H01L23/00 , H05K3/34 , H05K3/40 , H05K1/02
CPC分类号： H01L24/16 , H01L24/11 , H01L2224/16225 , H01L2924/14 , H01L2924/181 , H05K1/0271 , H05K3/3436 , H05K3/4007 , Y02P70/613 , H01L2924/00012 , H01L2924/00
摘要： Provided is a stress-relieving, second-level interconnect structure that is low-cost and accommodates thermal coefficient of expansion (TCE) mismatch between low-TCE packages and printed circuit boards (PCBs). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, thereby enhancing compliance between the two electronic components.
摘要翻译：提供了一种应力消除的二级互连结构，其低成本并适应低TCE封装和印刷电路板（PCB）之间的热膨胀系数（TCE）不匹配。所述互连结构至少包括第一焊盘，支撑柱和焊料凸块，其中第一焊盘和支撑柱可操作以吸收基本上所有的塑性应变，从而增强两个电子部件之间的顺应性。

5. 发明授权

US08536695B2 Chip-last embedded interconnect structures 有权
标题翻译：最后嵌入式互连结构
公开(公告)号：US08536695B2
公开(公告)日：2013-09-17
申请号：US13415503
申请日：2012-03-08
申请人： Fuhan Liu , Nitesh Kumbhat , Venkatesh Sundaram , Rao R. Tummala
发明人： Fuhan Liu , Nitesh Kumbhat , Venkatesh Sundaram , Rao R. Tummala
IPC分类号： H01L23/12 , H01L21/4763 , H05K1/00 , H05K1/03
CPC分类号： H01L23/49827 , H01L23/13 , H01L23/49833 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2225/06517 , H01L2225/06572 , H01L2225/1029 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/15153 , H01L2924/15311 , H01L2224/05599
摘要： The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.
摘要翻译：本发明的各种实施例提供了一种新颖的芯片最后嵌入式结构，其中IC嵌入在一至两个金属层基板内。本发明的各种实施例与现有技术的其它二维和三维WLFO封装相当，因为实施例具有类似的封装厚度和XY形状因子，短互连长度，到芯片I / O的精细间距互连，用于将芯片I / O焊盘重新分配到球栅阵列（BGA）或焊盘阵列（LGA）的降低的层数，以及改进的热管理选项。

6. 发明授权

US07556189B2 Lead-free bonding systems 失效
标题翻译：无铅焊接系统
公开(公告)号：US07556189B2
公开(公告)日：2009-07-07
申请号：US11138011
申请日：2005-05-26
申请人： Ankur Aggarwal , Isaac Robin Abothu , Pulugurtha Markondeya Raj , Rao R. Tummala
发明人： Ankur Aggarwal , Isaac Robin Abothu , Pulugurtha Markondeya Raj , Rao R. Tummala
IPC分类号： H01L21/02 , B05D1/00
CPC分类号： H01L21/2885 , B23K35/007 , B23K35/262 , B23K35/34 , H01L21/76885 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/1147 , H01L2224/13099 , H01L2224/13147 , H01L2224/16 , H01L2224/29111 , H01L2224/81203 , H01L2224/81208 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/15311
摘要： Nano-structured interconnect formation and a reworkable bonding process using solder films. Large area fabrication of nano-structured interconnects is demonstrated at a very fine pitch. This technology can be used for pushing the limits of current flip chip bonding in terms of pitch, number of I/Os, superior combination of electrical and mechanical properties as well as reworkability. Sol-gel and electroless processes were developed to demonstrate film bonding interfaces between metallic pads and nano interconnects. Solution-derived nano-solder technology is an attractive low-cost method for several applications such as MEMS hermetic packaging, compliant interconnect bonding and bump-less nano-interconnects.
摘要翻译：纳米结构的互连结构和使用焊料薄膜的可再结合的焊接工艺。纳米结构互连的大面积制造以非常细的间距示出。该技术可用于推动当前倒装芯片接合的极限，其间距，I / O数量，电气和机械性能的优异组合以及可再加工性。开发了溶胶 - 凝胶和无电工艺，以证明金属焊盘和纳米互连之间的膜结合界面。解决方案衍生的纳米焊料技术是MEMS密封封装，兼容互连接合和无凸点纳米互连等多种应用的有吸引力的低成本方法。

7. 发明申请

US20080136035A1 HIGH-ASPECT-RATIO METAL-POLYMER COMPOSITE STRUCTURES FOR NANO INTERCONNECTS 失效
标题翻译：用于纳米互连的高比例金属聚合物复合结构
公开(公告)号：US20080136035A1
公开(公告)日：2008-06-12
申请号：US11845384
申请日：2007-08-27
申请人： Ankur Aggarwal , Pulugurtha Markondeya Raj , Rao R. Tummala
发明人： Ankur Aggarwal , Pulugurtha Markondeya Raj , Rao R. Tummala
IPC分类号： H01L23/48
CPC分类号： B81C1/00619 , Y10S977/888 , Y10S977/89
摘要： A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. Other embodiments are also claimed and described.
摘要翻译：将高纵横比聚合物结构与无电镀铜结合在一起的低温工艺，以制造横向兼容的MEMS结构。这些结构可用作IC封装互连，可以导致可靠，低成本和高性能的纳米晶圆级封装。使用等离子体蚀刻制造具有低应力，高韧性和强度的高纵横比低CTE聚酰亚胺结构。调整干蚀刻工艺以产生高于80度的壁角，导致高于4的纵横比。蚀刻工艺还导致在聚合物结构的侧壁上进行选择性无电镀的粗糙化侧壁。这些制造的结构显示了作为IC封装纳米互连的界面处的应力减小和优异的可靠性。来自MEMS制造技术的金属涂层聚合物结构可为晶圆级封装提供低成本的高性能解决方案。还要求保护和描述其它实施例。

8. 发明授权

US07262075B2 High-aspect-ratio metal-polymer composite structures for nano interconnects 有权
标题翻译：用于纳米互连的高纵横比金属 - 聚合物复合结构
公开(公告)号：US07262075B2
公开(公告)日：2007-08-28
申请号：US11032301
申请日：2005-01-10
申请人： Ankur Aggarwal , Pulugurtha Markondeya Raj , Rao R. Tummala
发明人： Ankur Aggarwal , Pulugurtha Markondeya Raj , Rao R. Tummala
IPC分类号： H01L21/00
CPC分类号： B81C1/00619 , Y10S977/888 , Y10S977/89
摘要： A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging.
摘要翻译：将高纵横比聚合物结构与无电镀铜结合在一起的低温工艺，以制造横向兼容的MEMS结构。这些结构可用作IC封装互连，可以导致可靠，低成本和高性能的纳米晶圆级封装。使用等离子体蚀刻制造具有低应力，高韧性和强度的高纵横比低CTE聚酰亚胺结构。调整干蚀刻工艺以产生高于80度的壁角，导致高于4的纵横比。蚀刻工艺还导致在聚合物结构的侧壁上进行选择性无电镀的粗糙化侧壁。这些制造的结构显示了作为IC封装纳米互连的界面处的应力减小和优异的可靠性。来自MEMS制造技术的金属涂层聚合物结构可为晶圆级封装提供低成本的高性能解决方案。

9. 发明授权

US07557448B2 High-aspect-ratio metal-polymer composite structures for nano interconnects 失效
标题翻译：用于纳米互连的高纵横比金属 - 聚合物复合结构
公开(公告)号：US07557448B2
公开(公告)日：2009-07-07
申请号：US11845384
申请日：2007-08-27
申请人： Ankur Aggarwal , Pulugurtha Markondeya Raj , Rao R. Tummala
发明人： Ankur Aggarwal , Pulugurtha Markondeya Raj , Rao R. Tummala
IPC分类号： H01L23/48
CPC分类号： B81C1/00619 , Y10S977/888 , Y10S977/89
摘要： A low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures can be used as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. These fabricated structures show reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. Other embodiments are also claimed and described.
摘要翻译：将高纵横比聚合物结构与无电镀铜结合在一起的低温工艺，以制造横向兼容的MEMS结构。这些结构可用作IC封装互连，可以导致可靠，低成本和高性能的纳米晶圆级封装。使用等离子体蚀刻制造具有低应力，高韧性和强度的高纵横比低CTE聚酰亚胺结构。调整干蚀刻工艺以产生高于80度的壁角，导致高于4的纵横比。蚀刻工艺还导致在聚合物结构的侧壁上进行选择性无电镀的粗糙化侧壁。这些制造的结构显示了作为IC封装纳米互连的界面处的应力减小和优异的可靠性。来自MEMS制造技术的金属涂层聚合物结构可为晶圆级封装提供低成本的高性能解决方案。还要求保护和描述其它实施例。

10. 发明申请

US20120104603A1 INTERCONNECT ASSEMBLIES AND METHODS OF MAKING AND USING SAME 有权
标题翻译：互连组件及其制造和使用方法
公开(公告)号：US20120104603A1
公开(公告)日：2012-05-03
申请号：US13383727
申请日：2010-07-13
申请人： Nitesh Kumbhat , Abhishek Choudhury , Venky Sundaraman , Rao R. Tummala
发明人： Nitesh Kumbhat , Abhishek Choudhury , Venky Sundaraman , Rao R. Tummala
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/81 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/75 , H01L2224/0401 , H01L2224/0558 , H01L2224/05624 , H01L2224/16225 , H01L2224/32225 , H01L2224/731 , H01L2224/73204 , H01L2224/75 , H01L2224/75252 , H01L2224/75301 , H01L2224/81208 , H01L2224/81801 , H01L2224/83192 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15747 , H01L2924/15788 , H05K3/305 , H05K3/323 , H05K3/3436 , Y02P70/613 , H01L2924/00014 , H01L2924/00
摘要： The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.
摘要翻译：本发明的各种实施例提供细间距，芯片到衬底互连组件，以及制造和使用组件的方法。组件通常包括具有管芯焊盘和设置在其上的凸块的半导体和其上设置有衬底焊盘的衬底。凸起构造成当凸块与衬底焊盘接触时将半导体的至少一部分与衬底的至少一部分电互连。此外，当凸块与衬底焊盘接触时，凸起的至少一部分和衬底焊盘的至少一部分变形，从而在它们之间产生非冶金结合。

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