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1. 发明授权

US09742382B2 Flip-flop for reducing dynamic power 有权
公开(公告)号：US09742382B2
公开(公告)日：2017-08-22
申请号：US14783761
申请日：2013-05-08
申请人： QUALCOMM INCORPORATED
发明人： Yanfei Cai , Qiang Dai , Shuangqu Huang
IPC分类号： H03K3/037 , H03K3/3562 , H03K3/012
CPC分类号： H03K3/35625 , H03K3/012
摘要： A flip-flop circuit may include a first latch and a second latch. The first latch, which may operate as a “master” latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an output terminal. The second latch, which may operate as a “slave” latch, includes a first input terminal connected directly to the output terminal of the first latch, a second input terminal to receive the clock signal, and an output terminal to provide an output signal. The first latch and the second latch are to be clocked on the same phase of the clock signal, thereby eliminating the need to include clock inversion circuits that generate complementary clock signals.

2. 发明授权

US09270270B2 Clock gating circuit for reducing dynamic power 有权
标题翻译：时钟选通电路，用于降低动态功耗
公开(公告)号：US09270270B2
公开(公告)日：2016-02-23
申请号：US14420230
申请日：2012-09-19
申请人： QUALCOMM INCORPORATED
发明人： Yanfei Cai , Ji Li , Qiang Dai
IPC分类号： H03K3/00 , H03K19/00 , H03K3/356
CPC分类号： H03K19/0016 , H03K3/356052
摘要： A clock-gating circuit is disclosed that may reduce unnecessary power consumption associated with clock distribution networks. For some embodiments, the clock-gating circuit includes a latch control circuit, a storage latch, and a logic gate. The control circuit has inputs to receive an input clock signal, a clock enable signal, and a clock gating control signal, and has an output terminal to generate a latch enable signal. The latch has a data terminal responsive to the clock enable signal, a latch enable terminal responsive to the latch enable signal, and an output to generate the clock gating control signal. The logic gate has inputs to receive the input clock signal and the clock gating control signal, and has an output terminal to generate an output clock signal. The clock-gating circuit may reduce power consumption during an enabled state by maintaining the latch enable signal at a constant logic state, thereby reducing dynamic power consumption by preventing internal logic gates from dynamically switching logic states while the input clock signal is gated.
摘要翻译：公开了可以减少与时钟分配网络相关联的不必要的功耗的时钟选通电路。对于一些实施例，时钟门控电路包括锁存控制电路，存储锁存器和逻辑门。控制电路具有接收输入时钟信号，时钟使能信号和时钟门控控制信号的输入端，并具有产生锁存使能信号的输出端子。锁存器具有响应于时钟使能信号的数据端子，响应于锁存使能信号的锁存器使能端子和产生时钟门控控制信号的输出端。逻辑门具有用于接收输入时钟信号和时钟门控控制信号的输入，并且具有用于产生输出时钟信号的输出端子。时钟门控电路可以通过将锁存器使能信号保持在恒定的逻辑状态来在使能状态下降低功耗，从而通过在输入时钟信号选通时防止内部逻辑门动态地切换逻辑状态来减少动态功耗。

3. 发明申请

US20150200669A1 CLOCK GATING CIRCUIT FOR REDUCING DYNAMIC POWER 有权
标题翻译：用于降低动态功率的时钟增益电路
公开(公告)号：US20150200669A1
公开(公告)日：2015-07-16
申请号：US14420230
申请日：2012-09-19
申请人： QUALCOMM INCORPORATED
发明人： Yanfei Cai , Ji Li , Qiang Dai
IPC分类号： H03K19/00 , H03K3/356
CPC分类号： H03K19/0016 , H03K3/356052
摘要： A clock-gating circuit is disclosed that may reduce unnecessary power consumption associated with clock distribution networks. For some embodiments, the clock-gating circuit includes a latch control circuit, a storage latch, and a logic gate. The control circuit has inputs to receive an input clock signal, a clock enable signal, and a clock gating control signal, and has an output terminal to generate a latch enable signal. The latch has a data terminal responsive to the clock enable signal, a latch enable terminal responsive to the latch enable signal, and an output to generate the clock gating control signal. The logic gate has inputs to receive the input clock signal and the clock gating control signal, and has an output terminal to generate an output clock signal. The clock-gating circuit may reduce power consumption during an enabled state by maintaining the latch enable signal at a constant logic state, thereby reducing dynamic power consumption by preventing internal logic gates from dynamically switching logic states while the input clock signal is gated.
摘要翻译：公开了可以减少与时钟分配网络相关联的不必要的功耗的时钟选通电路。对于一些实施例，时钟门控电路包括锁存控制电路，存储锁存器和逻辑门。控制电路具有接收输入时钟信号，时钟使能信号和时钟门控控制信号的输入端，并具有产生锁存使能信号的输出端子。锁存器具有响应于时钟使能信号的数据端子，响应于锁存使能信号的锁存器使能端子和产生时钟门控控制信号的输出端。逻辑门具有用于接收输入时钟信号和时钟门控控制信号的输入，并且具有用于产生输出时钟信号的输出端子。时钟门控电路可以通过将锁存器使能信号保持在恒定的逻辑状态来在使能状态下降低功耗，从而通过在输入时钟信号选通时防止内部逻辑门动态地切换逻辑状态来减少动态功耗。

4. 发明申请

US20160056801A1 FLIP-FLOP FOR REDUCING DYNAMIC POWER 有权
标题翻译：用于减少动力的FLIP-FLOP
公开(公告)号：US20160056801A1
公开(公告)日：2016-02-25
申请号：US14783761
申请日：2013-05-08
申请人： QUALCOMM INCORPORATED
发明人： Yanfei Cai , Qiang Dai , Shuangqu Huang
IPC分类号： H03K3/3562
CPC分类号： H03K3/35625 , H03K3/012
摘要： A flip-flop circuit may include a first latch and a second latch. The first latch, which may operate as a “master” latch, includes a first input terminal to receive a data signal, a second input terminal to receive a clock signal, and an output terminal. The second latch, which may operate as a “slave” latch, includes a first input terminal connected directly to the output terminal of the first latch, a second input terminal to receive the clock signal, and an output terminal to provide an output signal. The first latch and the second latch are to be clocked on the same phase of the clock signal, thereby eliminating the need to include clock inversion circuits that generate complementary clock signals.
摘要翻译：触发器电路可以包括第一锁存器和第二锁存器。可以作为“主”锁存器操作的第一锁存器包括用于接收数据信号的第一输入端子，用于接收时钟信号的第二输入端子和输出端子。可以作为“从”）锁存器操作的第二锁存器包括直接连接到第一锁存器的输出端子的第一输入端子，用于接收时钟信号的第二输入端子和用于提供输出信号的输出端子。第一锁存器和第二锁存器将在时钟信号的相同相位上被计时，从而不需要包括产生互补时钟信号的时钟反相电路。

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