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1. 发明申请

US20150347308A1 RECONFIGURABLE FETCH PIPELINE 有权
标题翻译：可重构FETCH管道
公开(公告)号：US20150347308A1
公开(公告)日：2015-12-03
申请号：US14287331
申请日：2014-05-27
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon
IPC分类号： G06F12/08
CPC分类号： G06F12/0884 , G06F9/30189 , G06F9/3802 , G06F9/3824 , G06F9/3851 , G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0857 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , G06F2212/283 , G06F2212/6012 , G06F2212/603 , Y02D10/13
摘要： A particular method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access.
摘要翻译：一种特定的方法包括基于存储在发布队列中的指令数量，执行单元的活动线程数量，或两者来选择第一高速缓存访问模式和第二高速缓存访问模式。该方法还包括执行第一高速缓存访问。当选择第一高速缓存访问模式时，执行第一高速缓存访问包括在执行标签访问之后执行标签访问并执行数据阵列访问。当选择第二高速缓存访问模式时，执行第一高速缓存访问包括与数据阵列访问并行地执行标签访问。

2. 发明申请

US20150324239A1 DYNAMIC LOAD BALANCING OF HARDWARE THREADS IN CLUSTERED PROCESSOR CORES USING SHARED HARDWARE RESOURCES, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：使用共享硬件资源的集群处理器芯片中的硬件线路的动态负载平衡以及相关电路，方法和计算机可读介质
公开(公告)号：US20150324239A1
公开(公告)日：2015-11-12
申请号：US14271812
申请日：2014-05-07
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon , Lin Wang
IPC分类号： G06F9/50 , G06F9/30
CPC分类号： G06F9/30098 , G06F9/3851 , G06F9/3891 , G06F9/5088
摘要： Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.
摘要翻译：公开了使用共享硬件资源的集群处理器核心中的硬件线程的动态负载平衡以及相关电路，方法和计算机可读介质。一方面，提供了包括控制单元的动态负载平衡电路。控制单元被配置为确定集群处理器核心的第一集群和第二集群之间是否存在次优负载条件。如果存在次优负载条件，则控制单元还被配置为经由共享硬件将第一集群的第一硬件线程的私有寄存器的内容传送到第二集群的第二硬件线程的私有寄存器第一个硬件线程和第二个硬件线程的资源。控制单元还被配置为经由共享硬件资源与第一硬件线程相关联的第一标识符与与第二硬件线程相关联的第二标识符进行交换。

3. 发明授权

US09529727B2 Reconfigurable fetch pipeline 有权
标题翻译：可重构抓取管道
公开(公告)号：US09529727B2
公开(公告)日：2016-12-27
申请号：US14287331
申请日：2014-05-27
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon
IPC分类号： G06F12/00 , G06F12/08 , G06F9/38 , G06F9/30
CPC分类号： G06F12/0884 , G06F9/30189 , G06F9/3802 , G06F9/3824 , G06F9/3851 , G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0857 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , G06F2212/283 , G06F2212/6012 , G06F2212/603 , Y02D10/13
摘要： A particular method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access.
摘要翻译：一种特定的方法包括基于存储在发布队列中的指令数量，执行单元的活动线程数量，或两者来选择第一高速缓存访问模式和第二高速缓存访问模式。该方法还包括执行第一高速缓存访问。当选择第一高速缓存访问模式时，执行第一高速缓存访问包括在执行标签访问之后执行标签访问并执行数据阵列访问。当选择第二高速缓存访问模式时，执行第一高速缓存访问包括与数据阵列访问并行地执行标签访问。

4. 发明授权

US11200058B2 Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media 有权
公开(公告)号：US11200058B2
公开(公告)日：2021-12-14
申请号：US14271812
申请日：2014-05-07
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon , Lin Wang
IPC分类号： G06F9/30 , G06F9/38 , G06F9/50
摘要： Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.

5. 发明授权

US11074076B2 Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media 有权
公开(公告)号：US11074076B2
公开(公告)日：2021-07-27
申请号：US14271812
申请日：2014-05-07
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon , Lin Wang
IPC分类号： G06F9/30 , G06F9/38 , G06F9/50
摘要： Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer readable media are disclosed. In one aspect, a dynamic load balancing circuit comprising a control unit is provided. The control unit is configured to determine whether a suboptimal load condition exists between a first cluster and a second cluster of a clustered processor core. If a suboptimal load condition exists, the control unit is further configured to transfer a content of private register(s) of a first hardware thread of the first cluster to private register(s) of a second hardware thread of the second cluster via shared hardware resources of the first hardware thread and the second hardware thread. The control unit is also configured to exchange a first identifier associated with the first hardware thread with a second identifier associated with the second hardware thread via the shared hardware resources.

6. 发明授权

US10007613B2 Reconfigurable fetch pipeline 有权
公开(公告)号：US10007613B2
公开(公告)日：2018-06-26
申请号：US15211315
申请日：2016-07-15
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon
IPC分类号： G06F12/00 , G06F12/0884 , G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0877 , G06F12/0864 , G06F9/38 , G06F9/30
CPC分类号： G06F12/0884 , G06F9/30189 , G06F9/3802 , G06F9/3824 , G06F9/3851 , G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0857 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , G06F2212/283 , G06F2212/6012 , G06F2212/603 , Y02D10/13
摘要： An apparatus includes an access mode selection circuit configured to select a cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit coupled to a cache, or both. The access mode selection circuit is further configured to generate an access mode signal based on the selected cache access mode. The apparatus further includes an address generation circuit configured to perform a cache access based on the access mode signal.

7. 发明申请

US20160328325A1 RECONFIGURABLE FETCH PIPELINE 有权
标题翻译：可重构FETCH管道
公开(公告)号：US20160328325A1
公开(公告)日：2016-11-10
申请号：US15211315
申请日：2016-07-15
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon
IPC分类号： G06F12/0855 , G06F12/0811
CPC分类号： G06F12/0884 , G06F9/30189 , G06F9/3802 , G06F9/3824 , G06F9/3851 , G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0857 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , G06F2212/283 , G06F2212/6012 , G06F2212/603 , Y02D10/13
摘要： An apparatus includes an access mode selection circuit configured to select a cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit coupled to a cache, or both. The access mode selection circuit is further configured to generate an access mode signal based on the selected cache access mode. The apparatus further includes an address generation circuit configured to perform a cache access based on the access mode signal.
摘要翻译：一种装置，包括：访问模式选择电路，被配置为基于存储在发布队列中的指令数量，耦合到高速缓存的执行单元的活动线程数量，或两者来选择高速缓存访问模式。访问模式选择电路还被配置为基于所选择的高速缓存访问模式生成访问模式信号。该装置还包括地址生成电路，被配置为基于访问模式信号执行高速缓存访问。

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