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1. 发明授权

US10007613B2 Reconfigurable fetch pipeline 有权
公开(公告)号：US10007613B2
公开(公告)日：2018-06-26
申请号：US15211315
申请日：2016-07-15
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon
IPC分类号： G06F12/00 , G06F12/0884 , G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0877 , G06F12/0864 , G06F9/38 , G06F9/30
CPC分类号： G06F12/0884 , G06F9/30189 , G06F9/3802 , G06F9/3824 , G06F9/3851 , G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0857 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , G06F2212/283 , G06F2212/6012 , G06F2212/603 , Y02D10/13
摘要： An apparatus includes an access mode selection circuit configured to select a cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit coupled to a cache, or both. The access mode selection circuit is further configured to generate an access mode signal based on the selected cache access mode. The apparatus further includes an address generation circuit configured to perform a cache access based on the access mode signal.

2. 发明授权

US09965185B2 Utilization of a distributed index to provide object memory fabric coherency 有权
公开(公告)号：US09965185B2
公开(公告)日：2018-05-08
申请号：US15001652
申请日：2016-01-20
申请人： ULTRATA, LLC
发明人： Steven J. Frank , Larry Reback
IPC分类号： G06F3/06 , G06F12/0877
CPC分类号： G06F3/0604 , G06F3/061 , G06F3/0631 , G06F3/0635 , G06F3/0638 , G06F3/064 , G06F3/0644 , G06F3/0647 , G06F3/0659 , G06F3/067 , G06F3/0683 , G06F3/0685 , G06F12/0817 , G06F12/0837 , G06F12/0877 , G06F2212/2542 , G06F2212/6012
摘要： Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

3. 发明申请

US20170091112A1 CONFIGURABLE CACHE ARCHITECTURE 审中-公开
公开(公告)号：US20170091112A1
公开(公告)日：2017-03-30
申请号：US14949946
申请日：2015-11-24
申请人： International Business Machines Corporation
发明人： Philip G. Emma
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0877 , G06F2212/221 , G06F2212/225 , G06F2212/6012
摘要： Embodiments relate to providing a configurable cache memory. An aspect includes configuring, via a cache configuration logic, a plurality of cache memories that make up the configurable cache memory into a selected mode, wherein the plurality of cache memories comprise physically separate memory modules, and wherein the plurality of cache memories are linked by the cache configuration logic. Another aspect includes operating the configurable cache memory in the selected mode, wherein the configurable cache memory is capable of operating in a plurality of modes.

4. 发明申请

US20160364337A1 MEMORY HAVING A STATIC CACHE AND A DYNAMIC CACHE 有权
标题翻译：具有静态高速缓存和动态缓存的存储器
公开(公告)号：US20160364337A1
公开(公告)日：2016-12-15
申请号：US14735498
申请日：2015-06-10
申请人： Micron Technology, Inc.
发明人： Christopher S. Hale , Sampath K. Ratnam , Kishore K. Muchherla
IPC分类号： G06F12/08 , G06F3/06
CPC分类号： G06F12/0897 , G06F3/0604 , G06F3/0634 , G06F3/0673 , G06F12/0238 , G06F12/0804 , G06F12/0871 , G06F2212/1008 , G06F2212/1016 , G06F2212/1024 , G06F2212/1036 , G06F2212/1041 , G06F2212/2515 , G06F2212/281 , G06F2212/6012 , G06F2212/608 , G06F2212/7203 , G06F2212/7206
摘要： The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.
摘要翻译：本公开包括具有静态高速缓存和动态高速缓存的存储器。多个实施例包括存储器，其中存储器包括被配置为作为静态单级单元（SLC）高速缓存进行操作的第一部分和被配置为当存储器的整个第一部分具有数据时被配置为作为动态SLC高速缓存操作的第二部分存储在其中。

5. 发明申请

US20160328325A1 RECONFIGURABLE FETCH PIPELINE 有权
标题翻译：可重构FETCH管道
公开(公告)号：US20160328325A1
公开(公告)日：2016-11-10
申请号：US15211315
申请日：2016-07-15
申请人： QUALCOMM Incorporated
发明人： Suresh Kumar Venkumahanti , Stephen Robert Shannon
IPC分类号： G06F12/0855 , G06F12/0811
CPC分类号： G06F12/0884 , G06F9/30189 , G06F9/3802 , G06F9/3824 , G06F9/3851 , G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0857 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , G06F2212/283 , G06F2212/6012 , G06F2212/603 , Y02D10/13
摘要： An apparatus includes an access mode selection circuit configured to select a cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit coupled to a cache, or both. The access mode selection circuit is further configured to generate an access mode signal based on the selected cache access mode. The apparatus further includes an address generation circuit configured to perform a cache access based on the access mode signal.
摘要翻译：一种装置，包括：访问模式选择电路，被配置为基于存储在发布队列中的指令数量，耦合到高速缓存的执行单元的活动线程数量，或两者来选择高速缓存访问模式。访问模式选择电路还被配置为基于所选择的高速缓存访问模式生成访问模式信号。该装置还包括地址生成电路，被配置为基于访问模式信号执行高速缓存访问。

6. 发明申请

US20160267008A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20160267008A1
公开(公告)日：2016-09-15
申请号：US15067658
申请日：2016-03-11
申请人： Kabushiki Kaisha Toshiba
发明人： Susumu TAKEDA
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0246 , G06F2212/6012 , Y02D10/13
摘要： A memory system has a first cache memory comprising a volatile memory, a second cache memory comprising a non-volatile memory with access speed slower than access speed of the volatile memory, and a reconfiguration control circuitry to switch between a first mode that uses the second cache memory as a cache memory in a lower layer than the first cache memory and a second mode that uses the first cache memory and the second cache memory as cache memories in an identical memory layer.
摘要翻译：存储器系统具有包括易失性存储器的第一高速缓存存储器，包括具有比易失性存储器的访问速度慢的访问速度的非易失性存储器的第二高速缓存存储器，以及重配置控制电路，用于在使用第二高速缓冲存储器作为比第一高速缓冲存储器低层的缓存存储器，以及第二模式，其将第一高速缓冲存储器和第二高速缓存存储器用作相同存储器层中的高速缓冲存储器。

7. 发明申请

US20160210082A1 IMPLEMENTATION OF AN OBJECT MEMORY CENTRIC CLOUD 审中-公开
标题翻译：对象记忆中心云的实现
公开(公告)号：US20160210082A1
公开(公告)日：2016-07-21
申请号：US15001494
申请日：2016-01-20
申请人： ULTRATA LLC
发明人： STEVEN FRANK , LARRY REBACK
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F3/061 , G06F3/0631 , G06F3/0635 , G06F3/0638 , G06F3/064 , G06F3/0644 , G06F3/0647 , G06F3/0659 , G06F3/067 , G06F3/0683 , G06F3/0685 , G06F12/0817 , G06F12/0837 , G06F12/0877 , G06F2212/2542 , G06F2212/6012
摘要： Embodiments of the invention provide systems and methods to implement an object memory fabric including hardware-based processing nodes having memory modules storing and managing memory objects created natively within the memory modules and managed by the memory modules at a memory layer, where physical address of memory and storage is managed with the memory objects based on an object address space that is allocated on a per-object basis with an object addressing scheme. Each node may utilize the object addressing scheme to couple to additional nodes to operate as a set of nodes so that all memory objects of the set are accessible based on the object addressing scheme, which defines invariant object addresses for the memory objects that are invariant with respect to physical memory storage locations and storage location changes of the memory objects within the memory module and across all modules interfacing the object memory fabric.
摘要翻译：本发明的实施例提供了一种用于实现包括基于硬件的处理节点的对象存储器结构的系统和方法，所述存储器模块存储和管理存储器模块内的本地创建并由存储器模块在存储器层处管理的存储器对象，其中存储器的物理地址并且基于使用对象寻址方案在每个对象基础上分配的对象地址空间来使用存储器对象来管理存储。每个节点可以使用对象寻址方案来耦合到附加节点以作为一组节点来操作，使得该集合的所有存储器对象可以基于对象寻址方案来访问，该对象寻址方案定义了对于不变的存储器对象的不变对象地址，关于存储器模块内的存储器对象的物理存储器存储位置和存储位置改变以及与对象存储器结构接口的所有模块。

8. 发明授权

US09367476B2 Memory management apparatus, method, and system 有权
标题翻译：内存管理装置，方法和系统
公开(公告)号：US09367476B2
公开(公告)日：2016-06-14
申请号：US14047579
申请日：2013-10-07
申请人： RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
发明人： Joonwon Lee , Jinkyu Jeong , Hwanju Kim , Jaeho Hwang
IPC分类号： G06F3/00 , G06F12/08 , G06F5/00
CPC分类号： G06F12/0897 , G06F12/0871 , G06F2212/6012
摘要： The present invention discloses a memory management apparatus, method, and system. An OS-based memory management apparatus associated with main memory includes a memory allocation controller configured to control a first memory region within the main memory such that the first memory region is used as a buffer cache depending on whether an input/output device is active or not in order to use the first memory region, allowing memory reservation for the input/output device, in the OS. The memory allocation controller controls the first memory region such that the first memory region is used as an eviction-based cache.
摘要翻译：本发明公开了一种存储器管理装置，方法和系统。与主存储器相关联的基于OS的存储器管理装置包括：存储器分配控制器，被配置为控制主存储器内的第一存储器区域，使得第一存储器区域用作缓冲器高速缓冲存储器，取决于输入/输出设备是否有效，不是为了使用第一存储器区域，允许在OS中输入/输出设备的存储器预留。存储器分配控制器控制第一存储器区域，使得第一存储器区域被用作基于驱逐的高速缓存。

9. 发明申请

US20160050112A1 DISTRIBUTED CACHING SYSTEMS AND METHODS 审中-公开
标题翻译：分布式缓存系统和方法
公开(公告)号：US20160050112A1
公开(公告)日：2016-02-18
申请号：US14825848
申请日：2015-08-13
申请人： PernixData, Inc.
发明人： Bryan Jeffrey Crowe , Akhilesh Joshi , Michal Ostrowski , Shyan-Ming Perng , Satyam Vaghani , Deepak Muley
IPC分类号： H04L12/24 , G06F11/20 , H04L29/08
CPC分类号： G06F3/0611 , G06F3/0613 , G06F3/0655 , G06F3/0688 , G06F9/46 , G06F9/5016 , G06F9/5077 , G06F11/1666 , G06F11/2082 , G06F11/2094 , G06F12/0804 , G06F12/0815 , G06F12/0868 , G06F2201/885 , G06F2209/508 , G06F2212/1032 , G06F2212/222 , G06F2212/6012 , G06F2212/657 , H04L41/0813 , H04L41/22 , H04L43/065 , H04L43/0817 , H04L67/2842 , H04L67/288
摘要： Example distributed caching systems and methods are described. In one implementation, a system has multiple host systems, each of which includes a cache resource that is accessed by one or more consumers. A management server is coupled to the multiple host systems and presents available cache resources and resources associated with available host systems to a user. The management server receives a user selection of at least one available cache resource and at least one host system. The selected host system is then configured to share the selected cache resource.
摘要翻译：描述了分布式缓存系统和方法的示例。在一个实现中，系统具有多个主机系统，每个主机系统包括由一个或多个消费者访问的高速缓存资源。管理服务器耦合到多个主机系统，并向用户呈现与可用主机系统相关联的可用高速缓存资源和资源。管理服务器接收至少一个可用高速缓存资源和至少一个主机系统的用户选择。然后，将所选择的主机系统配置为共享所选择的高速缓存资源。

10. 发明申请

US20150262696A1 MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM 审中-公开
标题翻译：存储系统的存储系统和控制方法
公开(公告)号：US20150262696A1
公开(公告)日：2015-09-17
申请号：US14475929
申请日：2014-09-03
申请人： Kabushiki Kaisha Toshiba
发明人： Akihiro SAKATA , Norikazu YOSHIDA , Toshikatsu HIDA , Yoshikazu TAKEYAMA , Shinichi KANNO
IPC分类号： G11C16/30 , G11C16/10 , G11C16/26
CPC分类号： G06F12/0868 , G06F1/3206 , G06F1/3275 , G06F1/3287 , G06F13/1668 , G06F2212/1028 , G06F2212/6012 , G11C2207/2227 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： According to one embodiment, a controller switches modes including a normal operating mode in which power resources of a volatile memory, a data storage unit, and a power control unit are all ON, a first mode in which the power resource of the volatile memory is OFF, and the power resources of the data storage unit and the power control unit are both ON, and a second mode in which the power resources of the volatile memory and the data storage unit are both OFF, and the power resource of the power control unit is ON. Upon receiving a low power consumption instruction command from a host, the controller stores management information to return to the normal operating mode into the volatile storage unit, and shifts the state of the memory system from the normal operating mode to the first mode.
摘要翻译：根据一个实施例，控制器切换包括易失性存储器，数据存储单元和功率控制单元的功率资源全部为ON的正常操作模式的模式，其中易失性存储器的功率资源为 OFF，数据存储单元和电源控制单元的电力资源都为ON，并且易失性存储器和数据存储单元的电力资源都为OFF的第二模式，以及功率控制的功率资源单位打开。在从主机接收到低功耗指令命令时，控制器将管理信息存储回到正常操作模式进入易失性存储单元，并将存储器系统的状态从正常操作模式转移到第一模式。

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