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1. 发明申请

US20080312890A1 SPECIFICATION VERIFICATION PROGRAM, COMPUTER-READABLE STORAGE MEDIUM STORING SPECIFICATION VERIFICATION PROGRAM, SPECIFICATION VERIFICATION APPARATUS, AND SPECIFICATION VERIFICATION METHOD 有权
标题翻译：规格验证程序，计算机可读存储介质存储规范验证程序，规范验证设备和规范验证方法
公开(公告)号：US20080312890A1
公开(公告)日：2008-12-18
申请号：US12136378
申请日：2008-06-10
申请人： Qiang ZHU , Hiroaki Iwashita , Koichiro Takayama , Tsuneo Nakata
发明人： Qiang ZHU , Hiroaki Iwashita , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06G7/48
CPC分类号： G06F8/10
摘要： Conditions necessary to be satisfied for execution of each use case from a use case description indicative of a requirements specification of the design object are acquired. Then a state satisfying the conditions, from among a set of states represented in a finite state machine model indicative of a design specification of the design object are detected. A presence or absence of an undetected state in the set of states in accordance with the detection is determined and output.
摘要翻译：获取从指示设计对象的要求规范的用例描述中执行每个用例所需要的条件。然后，检测从表示设计对象的设计规格的有限状态机模型中表示的一组状态中满足条件的状态。确定并输出根据检测的状态集合中的未检测状态的存在或不存在。

2. 发明授权

US08079001B2 Verification of requirements specification, design specification, and computer-readable storage medium apparatus, and method thereof 有权
标题翻译：验证要求规范，设计规范和计算机可读存储介质，设备及其方法
公开(公告)号：US08079001B2
公开(公告)日：2011-12-13
申请号：US12136378
申请日：2008-06-10
申请人： Qiang Zhu , Hiroaki Iwashita , Koichiro Takayama , Tsuneo Nakata
发明人： Qiang Zhu , Hiroaki Iwashita , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F8/10
摘要： Conditions necessary to be satisfied for execution of each use case from a use case description indicative of a requirements specification of the design object are acquired. Then a state satisfying the conditions, from among a set of states represented in a finite state machine model indicative of a design specification of the design object are detected. A presence or absence of an undetected state in the set of states in accordance with the detection is determined and output.
摘要翻译：获取从指示设计对象的要求规范的用例描述中执行每个用例所需要的条件。然后，检测从表示设计对象的设计规格的有限状态机模型中表示的一组状态中满足条件的状态。确定并输出根据检测的状态集合中的未检测状态的存在或不存在。

3. 发明授权

US07984403B2 Verification supporting system 有权
标题翻译：验证支持系统
公开(公告)号：US07984403B2
公开(公告)日：2011-07-19
申请号：US12359105
申请日：2009-01-23
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证目标电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

4. 发明申请

US20090276740A1 VERIFICATION SUPPORTING APPARATUS, VERIFICATION SUPPORTING METHOD, AND COMPUTER PRODUCT 有权
标题翻译：验证支持设备，验证支持方法和计算机产品
公开(公告)号：US20090276740A1
公开(公告)日：2009-11-05
申请号：US12335105
申请日：2008-12-15
申请人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
发明人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.
摘要翻译：在验证支持装置中，记录单元记录其中可能发生在待验证电路的寄存器中可能发生的状态转换的DIRW矩阵和关于与状态转换相对应的路径的有效性的信息，并且获取单元获取控制数据流图包括其中写入数据流图的控制流图。当指定用于验证的寄存器时，从控制数据流程图中提取其中描述的指定寄存器的数据流图。从提取的数据流图中，提取指示关于寄存器的数据流的路径。识别提取的路径的状态转换，并且如果在DIRW矩阵中设置状态转换，则将与DIRW矩阵和路径中设置的有效性有关的信息相关并输出。

5. 发明授权

US08312400B2 Verification supporting system 有权
标题翻译：验证支持系统
公开(公告)号：US08312400B2
公开(公告)日：2012-11-13
申请号：US13157534
申请日：2011-06-10
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证目标电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

6. 发明申请

US20110239172A1 VERIFICATION SUPPORTING SYSTEM 有权
标题翻译：验证支持系统
公开(公告)号：US20110239172A1
公开(公告)日：2011-09-29
申请号：US13157534
申请日：2011-06-10
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证目标电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

7. 发明授权

US08015519B2 Verification supporting apparatus, verification supporting method, and computer product 有权
标题翻译：验证支持设备，验证支持方式和计算机产品
公开(公告)号：US08015519B2
公开(公告)日：2011-09-06
申请号：US12335105
申请日：2008-12-15
申请人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
发明人： Akio Matsuda , Ryosuke Oishi , Koichiro Takayama , Tsuneo Nakata , Rafael Kazumiti Morizawa
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.
摘要翻译：在验证支持装置中，记录单元记录其中可能发生在待验证电路的寄存器中可能发生的状态转换的DIRW矩阵和关于与状态转换相对应的路径的有效性的信息，并且获取单元获取控制数据流图包括其中写入数据流图的控制流图。当指定用于验证的寄存器时，从控制数据流程图中提取其中描述的指定寄存器的数据流图。从提取的数据流图中，提取指示关于寄存器的数据流的路径。识别提取的路径的状态转换，并且如果在DIRW矩阵中设置状态转换，则将与DIRW矩阵和路径中设置的有效性有关的信息相关并输出。

8. 发明申请

US20090287965A1 VERIFICATION SUPPORTING SYSTEM 有权
标题翻译：验证支持系统
公开(公告)号：US20090287965A1
公开(公告)日：2009-11-19
申请号：US12359105
申请日：2009-01-23
申请人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
发明人： Ryosuke Oishi , Akio Matsuda , Koichiro Takayama , Tsuneo Nakata
IPC分类号： G06F11/34
CPC分类号： G06F17/5022 , G06F17/504
摘要： A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.
摘要翻译：从验证对象电路的配置指定要验证的验证目标寄存器，并且提取需要验证的模式作为关于指定的验证目标寄存器的覆盖标准。当提取模式时，准备一个DIRW矩阵，以指示包含在验证目标电路中的寄存器中的四个状态中声明，初始化，读取和写入中的可能发生的状态转换，并用于确定两个覆盖标准，矩阵覆盖标准和实施覆盖标准。

9. 发明授权

US6141633A Logical device verification method and apparatus 失效
标题翻译：逻辑设备验证方法和设备
公开(公告)号：US6141633A
公开(公告)日：2000-10-31
申请号：US31209
申请日：1998-02-26
申请人： Hiroaki Iwashita , Tsuneo Nakata
发明人： Hiroaki Iwashita , Tsuneo Nakata
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A verification apparatus which verifies whether or not a finite state machine indicating the operation of a synchronous sequential machine satisfies the property indicating the functional specification repeats the image computation in the M and the computation of a set product by q starting with the state set p when the finite state machine M, the subset q of the state of the M, and the subset p of the q are given; and checks the relation of the state set of the computation process. As a result, it can be determined, starting with a certain state in the p, whether or not a state transition path which eternally does not exceed the q exists.
摘要翻译：一种验证装置，其验证指示同步顺序机的操作的有限状态机是否满足指示功能规范的属性，重复M中的图像计算和从状态集p开始的q的计算，给出有限状态机M，M的状态的子集q和q的子集p; 并检查计算过程的状态集合的关系。结果，可以从p中的某个状态开始确定是否存在永久不超过q的状态转换路径。

10. 发明授权

US5708594A Automatic instruction string generation method and device for verifying processor operation model and logic 失效
标题翻译：用于验证处理器操作模型和逻辑的自动指令字符串生成方法和装置
公开(公告)号：US5708594A
公开(公告)日：1998-01-13
申请号：US433735
申请日：1995-05-03
申请人： Hiroaki Iwashita , Satoshi Kowatari , Tsuneo Nakata , Fumiyasu Hirose
发明人： Hiroaki Iwashita , Satoshi Kowatari , Tsuneo Nakata , Fumiyasu Hirose
IPC分类号： G06F9/38 , G06F11/22 , G06F11/267 , G06F12/00
CPC分类号： G06F11/2236
摘要： First, an initial operation model M.sub.0 of a pipeline is configured according to the pipeline configuration of a processor and the specification information about an instruction executed by the processor. Then, the number of the states of the initial operation model M.sub.0 is minimized to configure an operation model M. Based on the operation model M and a test state set H, listed are test instruction strings for the process in which the state of the operation model M indicates a transition from a predetermined input state to any of the test states contained in the test state set H without an occurrence of a conflict in the operation model M. A next time state, reached after the state of the operation model M has reached the test state of the test instruction string, is calculated and the next time state is input as a new input state to a test instruction string listing unit.
摘要翻译：首先，根据处理器的流水线配置和关于由处理器执行的指令的规范信息来配置流水线的初始操作模型M0。然后，将初始运行模型M0的状态数最小化以配置运算模型M.根据运算模型M和测试状态集合H列出的是用于运算状态的处理的测试指令串模型M表示从预定输入状态到包含在测试状态集合H中的任何测试状态的转换，而不会在操作模型M中发生冲突。在操作模型M的状态之后到达的下一个时间状态达到测试指令串的测试状态，并且将下一时间状态作为新的输入状态输入到测试指令串列表单元。

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