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1. 发明授权

US10891986B2 Semiconductor device 有权
公开(公告)号：US10891986B2
公开(公告)日：2021-01-12
申请号：US16375580
申请日：2019-04-04
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Tetsuo Fukushi , Hiroyuki Takahashi
IPC分类号： G11C5/06 , G11C7/10 , G11C8/06 , G11C7/06
摘要： The subject in the past is that there are a large number of data wirings in a semiconductor device including multiple memory cell arrays and that the area occupied by the data wirings is large. In a selected memory cell array among multiple memory cell arrays, a data wiring functions as a local wiring that transmits the data of the selected memory cell. In a memory cell array that is not selected among the memory cell arrays and is located between a data circuit and the selected memory cell array, the data wiring functions as a global wiring that transmits the data of a memory cell of the selected memory cell array.

2. 发明授权

US10714154B2 Semiconductor integrated circuit device and semiconductor device 有权
公开(公告)号：US10714154B2
公开(公告)日：2020-07-14
申请号：US16794907
申请日：2020-02-19
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Hiroyuki Takahashi , Muneaki Matsushige
IPC分类号： G11C5/14 , G11C7/06 , H01L27/108 , G11C11/409 , G11C7/08 , G11C11/4091 , G11C11/4074
摘要： Even when a driven circuit has a large-scale load, a small-scale step-down driver circuit can supply an internal potential to the driven circuit at high speed. A semiconductor integrated circuit device includes a step-down driver circuit which supplies, to a driven circuit to be driven by an internal potential lower than an external potential supplied from an external power supply, the internal potential. The step-down driver circuit includes an NMOS transistor having a drain coupled to an external power supply terminal to be coupled to the external power supply and a source to be coupled to a voltage supply point of the driven circuit and a driver circuit to drive the gate of the NMOS transistor.

3. 发明授权

US09620175B2 Semiconductor memory 有权
公开(公告)号：US09620175B2
公开(公告)日：2017-04-11
申请号：US15019739
申请日：2016-02-09
申请人： Renesas Electronics Corporation
发明人： Hiroyuki Takahashi
IPC分类号： G11C5/06 , G11C11/4091 , G11C11/419 , G11C11/4094 , G11C7/12 , G11C11/4097
CPC分类号： G11C5/06 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C11/419 , G11C2207/005
摘要： A semiconductor memory including a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair in which the sense amplifier includes; precharging transistors each having a diffusion layer and precharging the bit line pair, and switching transistors each having a diffusion layer formed integrally with the diffusion layer of the precharging transistor for selectively connecting the plurality of the bit line pairs to a common bus line.

4. 发明授权

US09406352B2 Semiconductor memory with sense amplifier 有权
公开(公告)号：US09406352B2
公开(公告)日：2016-08-02
申请号：US14797397
申请日：2015-07-13
申请人： Renesas Electronics Corporation
发明人： Hiroyuki Takahashi
IPC分类号： G11C7/06 , G11C11/4094 , G11C11/4097 , G11C5/02 , G11C7/08 , G11C11/4091 , H01L27/02 , H01L27/105 , H01L27/108 , G11C11/408
CPC分类号： G11C7/06 , G11C5/025 , G11C7/065 , G11C7/08 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/065 , H01L27/0207 , H01L27/105 , H01L27/10897
摘要： In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

5. 发明申请

US20160163357A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20160163357A1
公开(公告)日：2016-06-09
申请号：US15019739
申请日：2016-02-09
申请人： Renesas Electronics Corporation
发明人： Hiroyuki Takahashi
IPC分类号： G11C5/06 , G11C11/4091
CPC分类号： G11C5/06 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C11/419 , G11C2207/005
摘要： A semiconductor memory including a memory cell array having a plurality of memory cells, a plurality of bit line pairs which are disposed corresponding to respective columns of the memory cell array, and sense amplifiers which are disposed in plurality corresponding to the plurality of bit line pairs for amplifying a potential difference between the bit line pair in which the sense amplifier includes; precharging transistors each having a diffusion layer and precharging the bit line pair, and switching transistors each having a diffusion layer formed integrally with the diffusion layer of the precharging transistor for selectively connecting the plurality of the bit line pairs to a common bus line.
摘要翻译：一种半导体存储器，包括具有多个存储单元的存储单元阵列，对应于存储单元阵列的相应列设置的多个位线对以及与多个位线对相对配置的多个读出放大器用于放大读出放大器包括的位线对之间的电位差; 每个具有扩散层和对位线对进行预充电的预充电晶体管，以及各自具有与预充电晶体管的扩散层一体形成的扩散层的开关晶体管，用于选择性地将多个位线对连接到公共总线。

6. 发明授权

US09299797B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US09299797B2
公开(公告)日：2016-03-29
申请号：US14850062
申请日：2015-09-10
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Hiroyuki Takahashi , Seiya Yamano
IPC分类号： G11C7/02 , H01L29/423 , H01L27/108
CPC分类号： H01L29/42376 , G11C7/12 , G11C7/18 , H01L21/823437 , H01L27/0207 , H01L27/088 , H01L27/10897 , H01L29/1095
摘要： A semiconductor memory device includes a pair of bit lines connected to a plurality of memory cells, a first transistor connected between the pair of bit lines, a second transistor between at least one of the pair of bit lines and a first power supply voltage line, and a diffusion layer region shared between the first transistor and the second transistor, and connected to the one of the pair of bit lines. A gate of the first transistor and a gate of the second transistor are connected to each other. A gate of the first transistor is provided such that both a direction of a gate width of the first transistor and a direction of a gate width of second transistor are on one identical extension line.
摘要翻译：半导体存储器件包括连接到多个存储单元的一对位线，连接在该对位线之间的第一晶体管，位于一对位线中的至少一个与第一电源电压线之间的第二晶体管，以及在所述第一晶体管和所述第二晶体管之间共享并连接到所述一对位线之一中的扩散层区域。第一晶体管的栅极和第二晶体管的栅极彼此连接。提供第一晶体管的栅极，使得第一晶体管的栅极宽度的方向和第二晶体管的栅极宽度的方向都位于一条相同的延长线上。

7. 发明申请

US20150380507A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20150380507A1
公开(公告)日：2015-12-31
申请号：US14850062
申请日：2015-09-10
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Hiroyuki Takahashi , Seiya Yamano
IPC分类号： H01L29/423 , H01L27/108
CPC分类号： H01L29/42376 , G11C7/12 , G11C7/18 , H01L21/823437 , H01L27/0207 , H01L27/088 , H01L27/10897 , H01L29/1095
摘要： A semiconductor memory device includes a pair of bit lines connected to a plurality of memory cells, a first transistor connected between the pair of bit lines, a second transistor between at least one of the pair of bit lines and a first power supply voltage line, and a diffusion layer region shared between the first transistor and the second transistor, and connected to the one of the pair of bit lines. A gate of the first transistor and a gate of the second transistor are connected to each other. A gate of the first transistor is provided such that both a direction of a gate width of the first transistor and a direction of a gate width of second transistor are on one identical extension line.
摘要翻译：半导体存储器件包括连接到多个存储单元的一对位线，连接在该对位线之间的第一晶体管，位于一对位线中的至少一个与第一电源电压线之间的第二晶体管，以及在所述第一晶体管和所述第二晶体管之间共享并连接到所述一对位线之一中的扩散层区域。第一晶体管的栅极和第二晶体管的栅极彼此连接。提供第一晶体管的栅极，使得第一晶体管的栅极宽度的方向和第二晶体管的栅极宽度的方向都位于一条相同的延长线上。

8. 发明授权

US09111590B2 Semiconductor memory with sense amplifier 有权
标题翻译：具有读出放大器的半导体存储器
公开(公告)号：US09111590B2
公开(公告)日：2015-08-18
申请号：US14576992
申请日：2014-12-19
申请人： Renesas Electronics Corporation
发明人： Hiroyuki Takahashi
IPC分类号： G11C7/06 , G11C5/02 , G11C11/408 , H01L27/02 , G11C11/4091 , G11C7/08 , H01L27/108
CPC分类号： G11C7/06 , G11C5/025 , G11C7/065 , G11C7/08 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/065 , H01L27/0207 , H01L27/105 , H01L27/10897
摘要： In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.
摘要翻译：在示例性方面，本发明提供一种半导体存储器件，包括驱动与存储器单元连接的位线的读出放大器和向读出放大器提供电源的驱动晶体管，其中读出放大器被排成行并构成布置第一导电类型的晶体管的第一读出放大器行和布置有第二导电类型的晶体管的第二读出放大器行，并且驱动器晶体管构成至少一个晶体管列，其包括第一驱动晶体管对应于第一读出放大器行的第一导电类型和对应于第一读出放大器行和第二读出放大器行之间的第二读出放大器行的第二导电类型的第二驱动器晶体管。

9. 发明申请

US20150041922A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20150041922A1
公开(公告)日：2015-02-12
申请号：US14524966
申请日：2014-10-27
申请人： Renesas Electronics Corporation
发明人： Hiroyuki Takahashi , Seiya Yamano
IPC分类号： H01L27/108 , H01L29/10 , H01L27/088
CPC分类号： H01L29/42376 , G11C7/12 , G11C7/18 , H01L21/823437 , H01L27/0207 , H01L27/088 , H01L27/10897 , H01L29/1095
摘要： A semiconductor integrated circuit device includes a pair of complementary signal lines, a first transistor including a gate, a source, and a drain, one of the source and the drain of the first transistor being coupled to one of the pair of the complementary signal lines, and a second transistor including a gate, a source, and a drain, the gate of the second transistor being coupled to the gate of the first transistor, one of a source and a drain of the second transistor coupled to an other of the source and the drain of the first transistor, and an other of the source and the drain of the second transistor being coupled to the other of the pair of the complementary signal lines. A direction of a gate width of the first transistor is different from a direction of a gate width of the second transistor.
摘要翻译：半导体集成电路器件包括一对互补信号线，包括栅极，源极和漏极的第一晶体管，第一晶体管的源极和漏极之一耦合到该对互补信号线之一以及包括栅极，源极和漏极的第二晶体管，所述第二晶体管的栅极耦合到所述第一晶体管的栅极，所述第二晶体管的源极和漏极中的一个耦合到所述源极的另一个并且第一晶体管的漏极和第二晶体管的源极和漏极中的另一个耦合到该对互补信号线中的另一个。第一晶体管的栅极宽度的方向与第二晶体管的栅极宽度的方向不同。

10. 发明授权

US08804454B2 Word line selection circuit and row decoder 有权
标题翻译：字线选择电路和行解码器
公开(公告)号：US08804454B2
公开(公告)日：2014-08-12
申请号：US13741647
申请日：2013-01-15
申请人： Renesas Electronics Corporation
发明人： Hiroyuki Takahashi , Masahiro Yoshida , Noriaki Takeda
IPC分类号： G11C8/08
CPC分类号： G11C13/0028 , G11C8/08 , G11C8/10
摘要： A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.
摘要翻译：本发明的第一示例性方面是字线选择电路，其中输入由电源电压和低于地电压的第一电压组成的地址解码信号，并且由第一电压和第一电压组成的字线选择信号高于电源电压的第二电压不是通过根据地址解码信号的电平移位电路输出的。

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