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1. 发明授权

US11070168B2 Oscillator circuit 有权
公开(公告)号：US11070168B2
公开(公告)日：2021-07-20
申请号：US16876500
申请日：2020-05-18
申请人： ROHM CO., LTD.
发明人： Masanobu Tsuji
IPC分类号： H03B5/04 , H03B5/24
摘要： A variable-frequency oscillator generates an oscillator clock having a frequency that corresponds to a control signal. A programmable frequency divider divides the oscillator clock, so as to generate a divided clock. A F/V converter circuit includes a capacitor and a switch that switches at a frequency that corresponds to the divided clock, and generates a detection voltage that corresponds to a reference current. A reference voltage source outputs a reference voltage that corresponds to the electric potential that occurs at the resistor due to a reference current. A feedback circuit adjusts a control signal such that the detection voltage approaches the reference voltage. A correction circuit changes the frequency-dividing ratio of the programmable frequency divider based on a modulation signal modulated according to a correction coefficient that corresponds to the temperature.

2. 发明授权

US11128256B2 Oscillator circuit 有权
公开(公告)号：US11128256B2
公开(公告)日：2021-09-21
申请号：US16832562
申请日：2020-03-27
申请人： ROHM CO., LTD.
发明人： Masanobu Tsuji
IPC分类号： H03B5/12 , H03L7/099 , G01R19/165 , H03K5/24 , H02M3/07 , G01R23/09
摘要： A frequency variable oscillator generates a clock having a frequency according to a control signal. A reference current source generates a reference current. A path selector distributes the reference current to a first path and a second path in a time-sharing manner in synchronization with the clock. An F/V conversion circuit includes a capacitor connected to the first path, and charges or discharges the capacitor with the reference current and generates a detection voltage. The reference voltage source includes a resistor connected to the second path, and outputs a reference voltage according to a voltage across the resistor. A feedback circuit adjusts a control signal so that the detection voltage approaches the reference voltage.

3. 发明授权

US11070217B2 Phase locked loop circuit 有权
公开(公告)号：US11070217B2
公开(公告)日：2021-07-20
申请号：US17104274
申请日：2020-11-25
申请人： ROHM Co., LTD.
发明人： Masanobu Tsuji
IPC分类号： H03L7/099 , H03L7/081 , H03L7/089 , H03L7/093
摘要： Disclosed here is a PLL circuit that is an injection-locked PLL circuit. The PLL circuit includes a variable frequency oscillator configured in such a manner that a ring oscillator is formed during a period in which a window signal is negated and an injection edge based on a reference clock is allowed to be injected during a period in which the window signal is asserted, a feedback circuit that controls the variable frequency oscillator in such a manner that an oscillation frequency of the variable frequency oscillator gets closer to a target frequency according to the reference clock, and a window generator that receives an internal clock of the variable frequency oscillator and cuts out one pulse to generate the window signal.

4. 发明授权

US11211922B2 Voltage comparator for offset compensation 有权
公开(公告)号：US11211922B2
公开(公告)日：2021-12-28
申请号：US17084943
申请日：2020-10-30
申请人： ROHM Co., LTD.
发明人： Masanobu Tsuji
IPC分类号： H03K5/24 , H02M7/537 , G01R19/165 , H03K5/153 , H03K5/22 , H02M7/483
摘要： Disclosed herein is a voltage comparator including a first capacitor, a first inverter and a first switch connected in series and provided between both ends of the first capacitor, a second inverter connected in parallel with the first inverter, a second switch provided between an input and an output of the first inverter, a third switch provided between an input and an output of the second inverter, a second capacitor provided between the output of the first inverter and the input of the second inverter, a third capacitor provided between the output of the second inverter and the input of the first inverter, and a fourth switch provided in one of a position between an upper electrode of the first capacitor and a power supply line and a position between a lower electrode of the first capacitor and a ground line.

5. 发明授权

US10483956B2 Phase interpolator, timing generator, and semiconductor integrated circuit 有权
公开(公告)号：US10483956B2
公开(公告)日：2019-11-19
申请号：US16039921
申请日：2018-07-19
申请人： ROHM CO., LTD.
发明人： Masanobu Tsuji
IPC分类号： G06F1/04 , H03H11/26 , G06M1/10 , H03K5/156 , H03L7/07 , H03L7/081 , H03K5/00
摘要： During a period in which a first signal S1 and second signal S2 are both set to a first level, an initializing circuit initializes a capacitor voltage. Multiple circuit units are coupled in parallel between an intermediate line and a second line. An output circuit generates an output signal SOUT that changes level when the capacitor voltage crosses a predetermined threshold value VTH. Each circuit unit includes a resistor Rg and first path arranged in series between the intermediate and second lines and a second path parallel to the first path. The first path is configured to turn on when the first signal S1 is the second level and the corresponding bit of an input code is a first value. The second path is configured to turn on when the second signal S2 is the second level and the corresponding bit of the input code is a second value.

6. 发明授权

US11190190B2 Power supply circuit 有权
公开(公告)号：US11190190B2
公开(公告)日：2021-11-30
申请号：US16898951
申请日：2020-06-11
申请人： ROHM CO., LTD.
发明人： Masanobu Tsuji
IPC分类号： H03L7/07 , H03L7/099
摘要： An output terminal of a power supply circuit is coupled to a load. A control circuit charges multiple intermediate capacitors using an input voltage in a time-sharing manner. Furthermore, the control circuit selects at least one intermediate capacitor that is not being charged from among the multiple intermediate capacitors, and couples the intermediate capacitor thus selected to an output capacitor.

7. 发明授权

US09584125B2 Interface circuit 有权
标题翻译：接口电路
公开(公告)号：US09584125B2
公开(公告)日：2017-02-28
申请号：US14750337
申请日：2015-06-25
申请人： ROHM CO., LTD.
发明人： Masanobu Tsuji
IPC分类号： H03L5/00 , H03K19/0185 , H03K19/00 , H03K19/0175
CPC分类号： H03K19/018521 , H03K3/35613 , H03K19/0005 , H03K19/017509
摘要： An interface circuit receives an input signal IN having a first voltage amplitude from a first circuit, and outputs an output signal OUT having a second voltage amplitude to a second circuit. A level shifter comprises a first CMOS inverter and a second CMOS inverter which are cross-coupled, and a current limiting circuit that limits a current that flows through the first CMOS inverter and the second CMOS inverter, and converts the input signal IN into an intermediate signal INT which is a differential signal. A latch circuit receives the intermediate signal INT from the level shifter, and switches its state according to the positive signal and the negative signal of the intermediate signal INT.
摘要翻译：接口电路从第一电路接收具有第一电压幅度的输入信号IN，并将具有第二电压幅度的输出信号OUT输出到第二电路。电平移位器包括交叉耦合的第一CMOS反相器和第二CMOS反相器，以及限制流经第一CMOS反相器和第二CMOS反相器的电流的限流电路，并将输入信号IN转换成中间信号INT是差分信号。锁存电路从电平移位器接收中间信号INT，并根据中间信号INT的正信号和负信号切换其状态。

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