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1. 发明授权

US08165538B2 Systems and methods for implementing a harmonic rejection mixer 有权
标题翻译：用于实现谐波抑制混频器的系统和方法
公开(公告)号：US08165538B2
公开(公告)日：2012-04-24
申请号：US12145599
申请日：2008-06-25
申请人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
发明人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
IPC分类号： H04B1/04 , H04B15/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译：提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。

2. 发明授权

US08406707B2 Systems and methods for implementing a harmonic rejection mixer 有权
标题翻译：用于实现谐波抑制混频器的系统和方法
公开(公告)号：US08406707B2
公开(公告)日：2013-03-26
申请号：US13419741
申请日：2012-03-14
申请人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
发明人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
IPC分类号： H04B1/04 , H04B15/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译：提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。

3. 发明申请

US20120171973A1 SYSTEMS AND METHODS FOR IMPLEMENTING A HARMONIC REJECTION MIXER 有权
标题翻译：用于实施谐波抑制混合器的系统和方法
公开(公告)号：US20120171973A1
公开(公告)日：2012-07-05
申请号：US13419741
申请日：2012-03-14
申请人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
发明人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
IPC分类号： H04B1/04 , G06G7/00 , H04B1/26
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译：提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。

4. 发明申请

US20090325510A1 SYSTEMS AND METHODS FOR IMPLEMENTING A HARMONIC REJECTION MIXER 有权
标题翻译：用于实施谐波抑制混合器的系统和方法
公开(公告)号：US20090325510A1
公开(公告)日：2009-12-31
申请号：US12145599
申请日：2008-06-25
申请人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
发明人： Rajasekhar Pullela , Dmitriy Rozenblit , Hamid Firouzkouhi
IPC分类号： G06G7/161 , H03K5/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0047 , H03D2200/0086
摘要： Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.
摘要翻译：提供了用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统和方法的各种实施例。一个实施例是用于产生用于谐波抑制混频器的本地振荡器（LO）信号的系统。一个这样的系统包括本地振荡器，N分频分频器，除以三分频器和谐波抑制混频器。本地振荡器被配置为提供参考频率信号。 N分频器被配置为将参考频率信号除以值N并提供输出信号。三分频分频器被配置为接收除以N分频器的输出信号，并将输出信号分成三个相位偏移信号。谐波抑制混频器被配置为接收三个相位偏移信号并消除第三频率谐波。

5. 发明授权

US07483678B2 Single chip GSM/EDGE transceiver architecture with closed loop power control 失效
标题翻译：单芯片GSM / EDGE收发器架构，具有闭环功率控制
公开(公告)号：US07483678B2
公开(公告)日：2009-01-27
申请号：US11235907
申请日：2005-09-27
申请人： Dmitriy Rozenblit , Tirdad Sowlati , Rajasekhar Pullela
发明人： Dmitriy Rozenblit , Tirdad Sowlati , Rajasekhar Pullela
IPC分类号： H04B1/38
CPC分类号： H03B19/14 , H03G3/3047 , H03L7/081 , H03L7/087 , H03L7/0992 , H03L7/1978 , H03L7/23
摘要： A single chip GSM/EDGE transceiver comprises a fully differential receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired transmit and receive LO signals. The transceiver also comprises a transmitter having a closed power control loop, and a harmonic rejection modulator, the use thereof made possible by a frequency plan designed to allow the synthesizer to develop the transmit and receive LO signals without a frequency multiplier.
摘要翻译：单芯片GSM / EDGE收发器包括全差分接收链，接收链中的次谐波混频器，次谐波混频器被配置为接收射频（RF）输入信号和本地振荡器（LO）信号，该信号被相移一个标称45度的合成器，以及具有压控振荡器并具有至少一个分频器以产生所需发射和接收LO信号的合成器。收发器还包括具有闭合功率控制回路和谐波抑制调制器的发射机，其使用通过设计成允许合成器在没有倍频器的情况下开发发射和接收LO信号的频率计划成为可能。

6. 发明申请

US20070072577A1 Single chip GSM/EDGE transceiver architecture with closed loop power control 失效
标题翻译：单芯片GSM / EDGE收发器架构，具有闭环功率控制
公开(公告)号：US20070072577A1
公开(公告)日：2007-03-29
申请号：US11235907
申请日：2005-09-27
申请人： Dmitriy Rozenblit , Tirdad Sowlati , Rajasekhar Pullela
发明人： Dmitriy Rozenblit , Tirdad Sowlati , Rajasekhar Pullela
IPC分类号： H04B1/28 , H04M1/00 , H04B1/44
CPC分类号： H03B19/14 , H03G3/3047 , H03L7/081 , H03L7/087 , H03L7/0992 , H03L7/1978 , H03L7/23
摘要： A single chip GSM/EDGE transceiver comprises a fully differential receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired transmit and receive LO signals. The transceiver also comprises a transmitter having a closed power control loop, and a harmonic rejection modulator, the use thereof made possible by a frequency plan designed to allow the synthesizer to develop the transmit and receive LO signals without a frequency multiplier.
摘要翻译：单芯片GSM / EDGE收发器包括全差分接收链，接收链中的次谐波混频器，次谐波混频器被配置为接收射频（RF）输入信号和本地振荡器（LO）信号，该信号被相移一个标称45度的合成器，以及具有压控振荡器并具有至少一个分频器以产生所需发射和接收LO信号的合成器。收发器还包括具有闭合功率控制回路和谐波抑制调制器的发射机，其使用通过设计成允许合成器在没有倍频器的情况下开发发射和接收LO信号的频率计划成为可能。

7. 发明申请

US20070072556A1 Variable gain frequency multiplier 失效
标题翻译：可变增益倍频器
公开(公告)号：US20070072556A1
公开(公告)日：2007-03-29
申请号：US11348001
申请日：2006-02-06
申请人： Dmitriy Rozenblit , Rajasekhar Pullela , Tirdad Sowlati , Shahrzad Tadjpour
发明人： Dmitriy Rozenblit , Rajasekhar Pullela , Tirdad Sowlati , Shahrzad Tadjpour
IPC分类号： H04B1/38
CPC分类号： H03B19/14 , H03G3/3047 , H03L7/081 , H03L7/087 , H03L7/0992 , H03L7/1978 , H03L7/23
摘要： A variable gain frequency multiplier comprises a multiplier circuit and a control circuit configured to receive a power control signal, the power control signal being proportional to a power output signal.
摘要翻译：可变增益倍频器包括乘法器电路和被配置为接收功率控制信号的控制电路，功率控制信号与功率输出信号成比例。

8. 发明授权

US07515880B2 Variable gain frequency multiplier 失效
标题翻译：可变增益倍频器
公开(公告)号：US07515880B2
公开(公告)日：2009-04-07
申请号：US11348001
申请日：2006-02-06
申请人： Dmitriy Rozenblit , Rajasekhar Pullela , Tirdad Sowlati , Shahrzad Tadjpour
发明人： Dmitriy Rozenblit , Rajasekhar Pullela , Tirdad Sowlati , Shahrzad Tadjpour
IPC分类号： H04B1/38
CPC分类号： H03B19/14 , H03G3/3047 , H03L7/081 , H03L7/087 , H03L7/0992 , H03L7/1978 , H03L7/23
摘要： A variable gain frequency multiplier comprises a multiplier circuit and a control circuit configured to receive a power control signal, the power control signal being proportional to a power output signal.
摘要翻译：可变增益倍频器包括乘法器电路和被配置为接收功率控制信号的控制电路，功率控制信号与功率输出信号成比例。

9. 发明授权

US07398073B2 Low noise mixer 有权
标题翻译：低噪音混音器
公开(公告)号：US07398073B2
公开(公告)日：2008-07-08
申请号：US11220030
申请日：2005-09-06
申请人： Rajasekhar Pullela , Tirdad Sowlati , Dmitriy Rozenblit
发明人： Rajasekhar Pullela , Tirdad Sowlati , Dmitriy Rozenblit
IPC分类号： H04B1/26
CPC分类号： H04B1/28 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165 , H03D2200/0019 , H03D2200/0084
摘要： A low noise mixer comprises a first mixer core configured to receive a radio frequency (RF) input signal having an RF frequency, and a first local oscillator signal, wherein the first local oscillator signal is at a frequency that is nominally twice the frequency of the RF frequency, the first mixer core configured to switch the RF input signal to at least one secondary mixer core at a frequency that coincides with the frequency of the first local oscillator signal, the at least one secondary mixer core configured to receive the switched RF input signal and a second local oscillator signal, where the second local oscillator signal is at the same nominal frequency as the RF input signal, and wherein switching the RF input signal at the frequency of the first local oscillator signal substantially eliminates flicker noise associated with the down-conversion process.
摘要翻译：低噪声混频器包括被配置为接收具有RF频率的射频（RF）输入信号和第一本地振荡器信号的第一混频器核心，其中第一本地振荡器信号的频率是标称频率为 RF频率，所述第一混频器核心被配置为以与所述第一本机振荡器信号的频率一致的频率将所述RF输入信号切换到至少一个辅助混频器内核，所述至少一个辅助混频器核心被配置为接收所述切换的RF输入信号和第二本地振荡器信号，其中第二本机振荡器信号处于与RF输入信号相同的标称频率，并且其中以第一本地振荡器信号的频率切换RF输入信号基本上消除与下降相关联的闪烁噪声转换过程。

10. 发明授权

US08396436B2 System and method for closed loop power control calibration 有权
标题翻译：闭环功率控制校准的系统和方法
公开(公告)号：US08396436B2
公开(公告)日：2013-03-12
申请号：US13311355
申请日：2011-12-05
申请人： Dmitriy Rozenblit , Tirdad Sowlati , Dongsoo Daniel Koh , Rajasekhar Pullela
发明人： Dmitriy Rozenblit , Tirdad Sowlati , Dongsoo Daniel Koh , Rajasekhar Pullela
IPC分类号： H01Q11/12 , H04B1/04
CPC分类号： H03G3/3047 , H03G3/3042 , H04B17/21 , H04B2001/0416 , H04W52/06
摘要： A system for calibrating a closed power control loop includes an adder configured to inject a test signal into an adjustable element, a first peak detector configured to determine an amplitude of the injected test signal, a second peak detector configured to determine an amplitude of a return test signal, a comparator configured to determine the difference between the injected test signal and the return test signal, and a calibration engine configured to adjust the adjustable element so that the return test signal is offset from the injected test signal by a predetermined amount.
摘要翻译：用于校准闭合功率控制回路的系统包括被配置为将测试信号注入到可调元件中的加法器，被配置为确定注入的测试信号的幅度的第一峰值检测器，被配置为确定返回幅度的第二峰值检测器测试信号，比较器，被配置为确定注入的测试信号与返回测试信号之间的差异;以及校准引擎，被配置为调整可调节元件，使得返回测试信号偏离注入的测试信号预定量。

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