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1. 发明公开

US20230361761A1 FREQUENCY MULTIPLIER CIRCUIT 审中-公开
公开(公告)号：US20230361761A1
公开(公告)日：2023-11-09
申请号：US18143854
申请日：2023-05-05
申请人： Paragraf Limited
发明人： Ivor GUINEY , Thomas James BADCOCK , Robert WALLIS
IPC分类号： H03B19/14 , H03K5/00
CPC分类号： H03K5/00006 , H03B19/14
摘要： According to a first aspect of the disclosure, an integrated frequency multiplier circuit is provided. The circuit comprises a substrate, a strip of graphene, first and second electrode, a dielectric layer, a frequency input electrode, and a frequency output electrode. The strip of graphene has a uniform width provided on the substrate, the strip having a width x and a length y extending from a first end to a second end. The first and second electrodes are provided in electrical contact with the strip of graphene at the first and second ends of the strip of graphene respectively. The dielectric layer is provided on the strip of graphene, wherein the dielectric layer is provided across the width x of the strip of graphene. The frequency input electrode is formed on the dielectric layer, wherein the frequency input electrode is provided across the width x of the strip of graphene. The frequency input electrode is provided over the strip of graphene at a location closer to the first end of the strip of graphene than the second end. The frequency output electrode is provided in electrical contact with the strip of graphene at a location along the length of the strip of graphene between the second electrode and the frequency input electrode, spaced apart from the second electrode.

2. 发明授权

US10615158B2 Transition frequency multiplier semiconductor device 有权
公开(公告)号：US10615158B2
公开(公告)日：2020-04-07
申请号：US16100270
申请日：2018-08-10
申请人： Qorvo US, Inc.
发明人： Kevin Wesley Kobayashi
IPC分类号： H01L27/06 , H01L29/08 , H01L23/522 , H03B19/14 , H01L27/02 , H01L23/66
CPC分类号： H01L27/0629 , H01L23/5223 , H01L23/5228 , H01L29/0847 , H03B19/14 , H01L23/66 , H01L27/0207 , H01L2223/6672 , H01L2223/6688
摘要： A transition frequency multiplier semiconductor device having a first source region, a second source region, and a common drain region is disclosed. A first channel region is located between the first source region and the common drain region, and a second channel region is located between the second source region and the common drain region. A first gate region is located within the first channel region to control current flow between the first source region and the common drain region, while a second gate region is located within the second channel region to control current flow between the second source region and the common drain region. An inactive channel region is located between the first channel region and the second channel region such that the first channel region is electrically isolated from the second channel region.

3. 发明申请

US20170272062A1 CLOCK GENERATOR USING PASSIVE MIXER AND ASSOCIATED CLOCK GENERATING METHOD 审中-公开
公开(公告)号：US20170272062A1
公开(公告)日：2017-09-21
申请号：US15412048
申请日：2017-01-22
申请人： MEDIATEK INC.
发明人： Hsi-Liang Lu
IPC分类号： H03K5/135 , H03D7/14 , H04L7/033
CPC分类号： H03K5/135 , H03B19/14 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H04L7/0331
摘要： A clock generator has a buffer stage circuit, a passive mixer, and a channel selecting circuit. The buffer stage circuit receives a plurality of first reference clocks having a same first frequency but different phases. The passive mixer receives the first reference clocks from the buffer stage circuit, receives a plurality of second reference clocks having a same second frequency but different phases, and mixes the first reference clocks and the second reference clocks to generate a mixer output, wherein the second frequency is different from the first frequency. The channel selecting circuit extracts a plurality of third reference clocks from the mixer output, wherein the third reference clocks have a same third frequency but different phases, and the third frequency is different from the first frequency and the second frequency.

4. 发明申请

US20170149438A1 FACILITATION OF INCREASED LOCKING RANGE TRANSISTORS 有权
公开(公告)号：US20170149438A1
公开(公告)日：2017-05-25
申请号：US15425597
申请日：2017-02-06
申请人： City University of Hong Kong
发明人： Quan Xue , Haifeng Zhou , Kam Man Shum
IPC分类号： H03L7/099 , H01L49/02 , H03B19/14 , H01L21/768 , H01L29/66 , H01L21/8234 , H01L27/06
CPC分类号： H03L7/099 , H01L21/768 , H01L21/76895 , H01L21/823475 , H01L23/645 , H01L27/0207 , H01L27/0641 , H01L27/088 , H01L28/10 , H01L29/0696 , H01L29/4238 , H01L29/78 , H03B5/1212 , H03B5/1228 , H03B19/14 , H03D3/24
摘要： Transistors can be used for a variety of electronic-based applications. Therefore, transistor efficiency and performance is of importance. An apparatus is presented herein to increase the locking range of transistors by leveraging cross-coupled injection transistors in conjunction with symmetry injection transistors. The transistor efficiency can also be increase by reducing a parasitic capacitance associated with the components of the transistor.

5. 发明申请

US20170131391A1 DETECTOR GENERATING A DISPLACEMENT SIGNAL BY INJECTION LOCKING AND INJECTION PULLING 有权
公开(公告)号：US20170131391A1
公开(公告)日：2017-05-11
申请号：US15415832
申请日：2017-01-25
申请人： RichWave Technology Corp.
发明人： Tse-Peng Chen
IPC分类号： G01S11/10
CPC分类号： G01S11/10 , G01S7/034 , G01S7/35 , G01S13/536 , H03B19/14 , H03B2200/0074 , H03B2200/0082 , H03B2200/0088 , H03L7/0802 , H03L7/099 , H04L1/0053
摘要： A detector includes a frequency multiplier and a transceiving node. The frequency multiplier includes a first terminal, a second terminal and an output terminal. The first terminal is used to receive a first injection signal having a first frequency. The output terminal is used to output an output signal. The second terminal is used to receive a second injection signal having a second frequency. The frequency multiplier is used to output the output signal at a frequency substantially equal to a multiple of the first frequency by injection locking and pull the output signal to the second frequency by injection pulling. The transceiving node is coupled to the output terminal and the second terminal of the frequency multiplier. The transceiving node is used to transmit the output signal, and receive a received signal having a third frequency. The received signal is used to update the second injection signal.

6. 发明授权

US09577575B2 Injection locked frequency divider capable of adjusting oscillation frequency 有权
标题翻译：注入锁定分频器，可调节振荡频率
公开(公告)号：US09577575B2
公开(公告)日：2017-02-21
申请号：US14966294
申请日：2015-12-11
申请人： Research & Business Foundation Sungkyunkwan University
发明人： Kang Yoon Lee , Sang Yun Kim , Young Jun Park , Dong Soo Lee
IPC分类号： H03K21/00 , H03B19/14 , H03K3/03
CPC分类号： H03B19/14 , H03B2200/007 , H03B2200/0074 , H03K3/0315 , H03K3/0322
摘要： An injection locked frequency divider is disclosed. The injection-locked frequency divider includes a sub-harmonic injection-locked oscillator, a reference clock divider, a counter, and a variable load resistor control unit. The sub-harmonic injection-locked oscillator has variable load resistors that are adjusted in response to a resistance adjustment signal, and, when oscillation frequency determined based on the magnitudes of the variable load resistors is a sub-harmonic of an injection signal, outputs signals having the oscillation frequency as divided output signals. The reference clock divider generates a count-enable signal from a reference clock signal according to a reference division ratio. The counter generates divided output count signals based on the divided output signals in response to the count-enable signal. The variable load resistor control unit compares target count values, determined based on the target frequencies of the divided output signals, with the divided output count signals, and outputs the resistance adjustment signal.
摘要翻译：公开了一种注入锁定分频器。注入锁定分频器包括子谐波注入锁定振荡器，参考时钟分频器，计数器和可变负载电阻控制单元。子谐波注入锁定振荡器具有响应于电阻调节信号而调节的可变负载电阻器，并且当基于可变负载电阻器的幅度确定的振荡频率是喷射信号的次谐波时，输出信号具有作为分频输出信号的振荡频率。参考时钟分频器根据参考分频比从参考时钟信号产生计数使能信号。计数器响应于计数使能信号，基于划分的输出信号产生分割的输出计数信号。可变负载电阻控制单元将根据划分的输出信号的目标频率确定的目标计数值与划分的输出计数信号进行比较，并输出电阻调节信号。

7. 发明授权

US09515638B2 Bipolar transistor frequency doublers at millimeter-wave frequencies 有权
公开(公告)号：US09515638B2
公开(公告)日：2016-12-06
申请号：US14617468
申请日：2015-02-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Wooram Lee , Alberto Valdes Garcia
IPC分类号： H03B19/14 , H03K5/00
CPC分类号： H03K5/00006 , H03B19/14
摘要： Methods for frequency multiplying include receiving a signal having an input frequency at a frequency multiplier comprising a pair of transistors; and selecting a harmonic in the signal by connecting the transistors to a common impedance through a respective collector impedance, wherein an output frequency at the harmonic between the collector impedances and the common impedance is an even integer multiple of an input frequency.

8. 发明授权

US09490784B2 Apparatus and method for generating quadrupled reference clock from single ended crystal oscillator 有权
标题翻译：从单端晶体振荡器产生四倍参考时钟的装置和方法
公开(公告)号：US09490784B2
公开(公告)日：2016-11-08
申请号：US14640672
申请日：2015-03-06
申请人： QUALCOMM Incorporated
发明人： Mohammad Bagher Vahid Far , Alireza Khalili , Yashar Rajavi , Amirpouya Kavousian
IPC分类号： H03B19/14 , H03K5/156 , H03K5/00 , H03B19/10
CPC分类号： H03K5/00006 , H03B19/10 , H03B19/14 , H03K5/1565
摘要： A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a first control voltage and a second control voltage for the first buffer and a third control voltage for the second buffer based on the output signal.
摘要翻译：提供了一种方法，装置和计算机程序产品。该装置根据第一时钟频率输出正弦信号，产生基于正弦信号的具有25％占空比的第一数字信号，产生基于正弦信号具有25％占空比的第二数字信号，第一数字信号和第二数字信号，以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且使组合数字信号的第二时钟频率加倍，以产生具有第三个时钟频率是第一个时钟频率的四倍。该装置还基于输出信号产生用于第一缓冲器的第一控制电压和第二控制电压以及第二缓冲器的第三控制电压。

9. 发明申请

US20150077163A1 DYNAMIC FREQUENCY DIVIDER CIRCUIT 有权
标题翻译：动态频率分路电路
公开(公告)号：US20150077163A1
公开(公告)日：2015-03-19
申请号：US14394116
申请日：2012-04-20
申请人： Akbar Ghazinour , Saverio Trotta
发明人： Akbar Ghazinour , Saverio Trotta
IPC分类号： H03B19/14 , H03L7/00
CPC分类号： H03B19/14 , H03F1/0205 , H03F3/45085 , H03F3/60 , H03F3/602 , H03F2200/423 , H03F2200/513 , H03F2200/543 , H03F2203/45612 , H03F2203/45652 , H03F2203/45668 , H03F2203/45702 , H03K23/667 , H03L7/00
摘要： The invention relates to a Frequency Divider Circuit for dividing an input RF signal to a frequency divided RF signal. The circuit comprises a RF pair, a switching-quad pair coupled in series with a transimpedance amplifier and a double pair of emitter followers. The circuit comprises coupling elements for providing first DC paths to first amplifier paths of the RF pair and for providing second DC paths to second amplifier paths of the series arrangement of the switching-quad pair and the transimpedance amplifier. The first DC paths are independent of the second DC paths. RF connections are provided to couple the first and the second amplifier paths for transferring a signal from the first amplifier paths to the second amplifier paths.
摘要翻译：本发明涉及一种用于将输入RF信号划分为分频RF信号的分频器电路。该电路包括RF对，与跨阻放大器和双对发射极跟随器串联耦合的开关四极对。该电路包括用于向RF对的第一放大器路径提供第一DC路径的耦合元件，以及用于向开关四对和跨阻放大器的串联布置的第二放大器路径提供第二DC路径。第一DC路径独立于第二DC路径。提供RF连接以耦合第一和第二放大器路径，用于将信号从第一放大器路径传送到第二放大器路径。

10. 发明授权

US08952733B2 Frequency multiplier circuit and system 有权
标题翻译：倍频电路和系统
公开(公告)号：US08952733B2
公开(公告)日：2015-02-10
申请号：US13951331
申请日：2013-07-25
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Fangping Fan
IPC分类号： H03B19/00 , H03B19/14
CPC分类号： H03B19/14
摘要： A frequency multiplier circuit includes a first signal input terminal, a second signal input terminal, an output terminal, a power source terminal, a ground terminal, a main control circuit which is connected to the first signal input terminal, the second signal input terminal, the power source terminal and the ground terminal, a reference circuit which is connected to the power source terminal and the ground terminal, and a frequency synthesis circuit which is connected to the main control circuit, the reference circuit, the output terminal, the power source terminal and the ground terminal.
摘要翻译：倍频电路包括第一信号输入端子，第二信号输入端子，输出端子，电源端子，接地端子，连接到第一信号输入端子的主控制电路，第二信号输入端子，电源端子和接地端子，连接到电源端子和接地端子的参考电路，以及连接到主控制电路，参考电路，输出端子，电源的频率合成电路端子和接地端子。

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