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1. 发明授权

US09646972B2 Methods of forming buried vertical capacitors and structures formed thereby 有权
公开(公告)号：US09646972B2
公开(公告)日：2017-05-09
申请号：US14912402
申请日：2013-09-25
申请人： Rajashree Baskaran , Kimin Jun , Patrick Morrow
发明人： Rajashree Baskaran , Kimin Jun , Patrick Morrow
IPC分类号： H01L27/108 , H01L49/02 , H01L27/06
CPC分类号： H01L27/10832 , H01L21/84 , H01L27/0629 , H01L27/0688 , H01L27/10861 , H01L27/10867 , H01L27/1087 , H01L28/20 , H01L28/87 , H01L28/91 , H01L29/945
摘要： Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.

2. 发明申请

US20130000117A1 LIQUID METAL INTERCONNECTS 有权
标题翻译：液体金属互连
公开(公告)号：US20130000117A1
公开(公告)日：2013-01-03
申请号：US13173933
申请日：2011-06-30
申请人： Rajashree Baskaran , Kimin Jun , Ting Zhong , Roy E. Swart , Paul B. Fischer
发明人： Rajashree Baskaran , Kimin Jun , Ting Zhong , Roy E. Swart , Paul B. Fischer
IPC分类号： H01R43/16
CPC分类号： G01R1/0416 , G01R1/06783 , H01R3/08 , Y10T29/49204
摘要： Embodiments of the invention provide methods for forming electrical connections using liquid metals. Electrical connections that employ liquid metals are useful for testing and validation of semiconductor devices. Electrical connections are formed between the probes of a testing interface and the electronic interface of a device under test through a liquid metal region. In embodiments of the invention, liquid metal interconnects are comprised of gallium or liquid metal alloys of gallium. The use of liquid metal contacts does not require a predetermined amount of force be applied in order to reliably make an electrical connection.
摘要翻译：本发明的实施例提供了使用液态金属形成电连接的方法。使用液态金属的电气连接对于半导体器件的测试和验证是有用的。通过液态金属区域在测试界面的探针和被测器件的电子接口之间形成电连接。在本发明的实施例中，液态金属互连由镓或镓的液态金属合金构成。为了可靠地进行电连接，使用液态金属触点不需要施加预定量的力。

3. 发明授权

US09835648B2 Liquid metal interconnects 有权
公开(公告)号：US09835648B2
公开(公告)日：2017-12-05
申请号：US13173933
申请日：2011-06-30
申请人： Rajashree Baskaran , Kimin Jun , Ting Zhong , Roy E. Swart , Paul B. Fischer
发明人： Rajashree Baskaran , Kimin Jun , Ting Zhong , Roy E. Swart , Paul B. Fischer
IPC分类号： G01R31/28 , G01R1/04 , H01R3/08 , G01R1/067
CPC分类号： G01R1/0416 , G01R1/06783 , H01R3/08 , Y10T29/49204
摘要： Embodiments of the invention provide methods for forming electrical connections using liquid metals. Electrical connections that employ liquid metals are useful for testing and validation of semiconductor devices. Electrical connections are formed between the probes of a testing interface and the electronic interface of a device under test through a liquid metal region. In embodiments of the invention, liquid metal interconnects are comprised of gallium or liquid metal alloys of gallium. The use of liquid metal contacts does not require a predetermined amount of force be applied in order to reliably make an electrical connection.

4. 发明申请

US20140264739A1 METHODS OF FORMING UNDER DEVICE INTERCONNECT STRUCTURES 有权
标题翻译：在设备互连结构下形成的方法
公开(公告)号：US20140264739A1
公开(公告)日：2014-09-18
申请号：US13798575
申请日：2013-03-13
申请人： Patrick Morrow , Don Nelson , Clair M. Webb , Kimin Jun , Il-Seok Son
发明人： Patrick Morrow , Don Nelson , Clair M. Webb , Kimin Jun , Il-Seok Son
IPC分类号： H01L23/48 , H01L27/04 , H01L21/02 , H01L21/82
CPC分类号： H01L23/535 , H01L21/2007 , H01L21/743 , H01L23/50 , H01L23/522 , H01L23/5286 , H01L24/18 , H01L27/1207
摘要： Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
摘要翻译：描述了在器件结构下形成微电子互连的方法。这些方法和结构可以包括在第一衬底中形成器件层，在第二衬底中形成至少一个布线层，然后将第一衬底与第二衬底耦合，其中第一衬底与第二衬底结合。

5. 发明申请

US20160197069A1 MONOLITHIC THREE-DIMENSIONAL (3D) ICs WITH LOCAL INTER-LEVEL INTERCONNECTS 有权
标题翻译：具有本地互联互连的单片三维（3D）IC
公开(公告)号：US20160197069A1
公开(公告)日：2016-07-07
申请号：US14778512
申请日：2013-06-25
申请人： Patrick Morrow , Kimin Jun , M. Clair Webb , Donald W. Nelson
发明人： Patrick Morrow , Kimin Jun , M. Clair Webb , Donald W. Nelson
IPC分类号： H01L27/06 , H01L29/78 , H01L23/538 , H01L27/11 , H01L21/822
CPC分类号： H01L27/0688 , H01L21/76895 , H01L21/76897 , H01L21/8221 , H01L21/823431 , H01L21/845 , H01L23/5386 , H01L27/0886 , H01L27/1104 , H01L27/1116 , H01L27/1211 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.
摘要翻译：使用一个或多个本地级间互连的单片3D IC，其与3D IC内的至少一个晶体管级上的至少一个晶体管的至少一个结构紧密集成。在某些实施例中，局部级间互连与至少一个晶体管的栅电极或源/漏区相交，并延伸穿过设置在3D IC中的第一和第二晶体管级之间的至少一个级间介电层。有利地，本地级间互连可以在3D IC的不同级别中的晶体管之间进行直接垂直连接，而不会横向绕过互连的上覆或下伏晶体管级的覆盖区（即，横向或平面区域）。

6. 发明授权

US10367070B2 Methods of forming backside self-aligned vias and structures formed thereby 有权
公开(公告)号：US10367070B2
公开(公告)日：2019-07-30
申请号：US15754804
申请日：2015-09-24
申请人： Intel Corporation , Patrick Morrow , Mauro J. Kobrinsky , Kimin Jun , Il-Seok Son , Paul B. Fischer
发明人： Patrick Morrow , Mauro J. Kobrinsky , Kimin Jun , Il-Seok Son , Paul B. Fischer
IPC分类号： H01L21/00 , H01L27/00 , H01L29/00 , H01L29/417 , H01L21/02 , H01L21/768 , H01L21/8234 , H01L23/522 , H01L23/528 , H01L27/088 , H01L29/08 , H01L29/10 , H01L29/165 , H01L29/66 , H01L29/78 , H01L21/84 , H01L27/12 , H01L21/265 , H01L21/306 , H01L21/324
摘要： Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

7. 发明授权

US09920438B2 Methods and apparatus for ultrathin catalyst layer for photoelectrode 有权
公开(公告)号：US09920438B2
公开(公告)日：2018-03-20
申请号：US13544940
申请日：2012-07-09
申请人： Kimin Jun , Joseph Jacobson
发明人： Kimin Jun , Joseph Jacobson
IPC分类号： C25B1/00 , C25B11/02 , C25B11/06 , C25B11/04 , H01G9/20
CPC分类号： C25B1/003 , C25B11/02 , C25B11/0452 , H01G9/2031 , H01G9/2036 , Y02E10/542 , Y02P20/135
摘要： In exemplary implementations of this invention, a photoelectrode includes a semiconductor for photocarrier generation, and a catalyst layer for altering the reaction rate in an adjacent electrolyte. The catalyst layer covers part of the semiconductor. The thickness of the catalyst layer is less than 60% of its minority carrier diffusion distance. If the photoelectrode is a photoanode, it has an OEP that is more than the potential of the valance band edge but less than the potential of the Fermi level of the semiconductor. If it is a photocathode, it has an RHE potential that is less than the potential of the conduction band edge but more than the potential of the Fermi level of the semiconductor. The absolute value of difference (OEP minus potential of valence band edge, or RHE potential minus potential of conduction band edge) is greater than zero and less than or equal to 0.2V.

8. 发明申请

US20130008495A1 Methods and Apparatus for Ultrathin Catalyst Layer for Photoelectrode 有权
标题翻译：用于光电极的超薄催化剂层的方法和装置
公开(公告)号：US20130008495A1
公开(公告)日：2013-01-10
申请号：US13544940
申请日：2012-07-09
申请人： Kimin Jun , Joseph Jacobson
发明人： Kimin Jun , Joseph Jacobson
IPC分类号： H01L31/0264 , H01L31/0376 , H01L31/0352 , H01L31/02 , H01G9/20
CPC分类号： C25B1/003 , C25B11/02 , C25B11/0452 , H01G9/2031 , H01G9/2036 , Y02E10/542 , Y02P20/135
摘要： In exemplary implementations of this invention, a photoelectrode includes a semiconductor for photocarrier generation, and a catalyst layer for altering the reaction rate in an adjacent electrolyte. The catalyst layer covers part of the semiconductor. The thickness of the catalyst layer is less than 60% of its minority carrier diffusion distance. If the photoelectrode is a photoanode, it has an OEP that is more than the potential of the valance band edge but less than the potential of the Fermi level of the semiconductor. If it is a photocathode, it has an RHE potential that is less than the potential of the conduction band edge but more than the potential of the Fermi level of the semiconductor. The absolute value of difference (OEP minus potential of valence band edge, or RHE potential minus potential of conduction band edge) is greater than zero and less than or equal to 0.2V.
摘要翻译：在本发明的示例性实施方案中，光电极包括用于光载体产生的半导体和用于改变相邻电解质中的反应速率的催化剂层。催化剂层覆盖半导体的一部分。催化剂层的厚度小于其少数载流子扩散距离的60％。如果光电极是光电阳极，则其具有超过有效带边缘的电位但小于半导体的费米能级的电位的OEP。如果它是一个光电阴极，它的RHE电位小于导带边缘的电位，但大于半导体费米能级的电位。差值的绝对值（OEP减去价带边缘的电位，或RHE电位减去导带边缘的电位）大于零且小于或等于0.2V。

9. 发明申请

US20150179664A1 HETEROGENEOUS SEMICONDUCTOR MATERIAL INTEGRATION TECHNIQUES 有权
标题翻译：异质半导体材料整合技术
公开(公告)号：US20150179664A1
公开(公告)日：2015-06-25
申请号：US14139954
申请日：2013-12-24
申请人： Alejandro X. Levander , Kimin Jun
发明人： Alejandro X. Levander , Kimin Jun
IPC分类号： H01L27/12 , H01L21/311 , H01L21/3105 , H01L21/02 , H01L21/762 , H01L21/265
CPC分类号： H01L27/1207 , H01L21/02002 , H01L21/02521 , H01L21/02634 , H01L21/02642 , H01L21/02647 , H01L21/265 , H01L21/31053 , H01L21/31111 , H01L21/76251 , H01L21/76254 , H01L27/1203 , H01L29/0649 , H01L29/26
摘要： Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands.
摘要翻译：公开了在初始衬底上的晶格失配的半导体材料层的异质外延生长的技术，以及将该层的无缺陷部分转移到处理晶片或其它合适的衬底以进行集成。根据一些实施例，转移可能导致在手柄晶片/衬底上存在岛状氧化物结构，每个具有嵌入其上表面内的晶格失配的半导体材料的无缺陷岛。每个无缺陷的半导体岛可以具有一个或多个晶面的边缘，并且随着其伴随的氧化物结构可提供用于集成的平坦表面。在一些情况下，第二不同的半导体材料的层可以在手柄晶片/衬底上异质外延生长以填充转移的岛周围的区域。在一些其它情况下，处理晶片/衬底本身可以被同侧外延生长以填充转移的岛周围的区域。

10. 发明申请

US20210202476A1 THREE-DIMENSIONAL INTEGRATED CIRCUITS (3DICS) INCLUDING BOTTOM GATE MOS TRANSISTORS WITH MONOCRYSTALLINE CHANNEL MATERIAL 有权
公开(公告)号：US20210202476A1
公开(公告)日：2021-07-01
申请号：US16728983
申请日：2019-12-27
申请人： Cheng-Ying Huang , Gilbert Dewey , Ashish Agrawal , Kimin Jun , Willy Rachmady , Zachary Geiger , Cory Bomberger , Ryan Keech , Koustav Ganguly , Anand Murthy , Jack Kavalieros
发明人： Cheng-Ying Huang , Gilbert Dewey , Ashish Agrawal , Kimin Jun , Willy Rachmady , Zachary Geiger , Cory Bomberger , Ryan Keech , Koustav Ganguly , Anand Murthy , Jack Kavalieros
IPC分类号： H01L27/06 , H01L21/683 , H01L21/8238 , H01L29/10 , H01L29/04 , H01L29/08 , H01L27/092
摘要： A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

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