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1. 发明申请

US20230075057A1 DYNAMICALLY CHANGING DATA ACCESS BANDWIDTH BY SELECTIVELY ENABLING AND DISABLING DATA LINKS 有权
公开(公告)号：US20230075057A1
公开(公告)日：2023-03-09
申请号：US17945863
申请日：2022-09-15
申请人： Rambus Inc.
发明人： Frederick A. WARE
IPC分类号： G06F1/3287 , G06F1/3234 , G06F13/16 , G06F1/3293
摘要： Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

2. 发明申请

US20220374306A1 SERIALIZING AND DESERIALIZING STAGE TESTING 有权
公开(公告)号：US20220374306A1
公开(公告)日：2022-11-24
申请号：US17840153
申请日：2022-06-14
申请人： Rambus Inc.
发明人： Angus William McLAREN , Robert A. HEATON , Aaron ALI , Frederick A. WARE
IPC分类号： G06F11/10 , H03M13/09
摘要： A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.

3. 发明申请

US20210326204A1 MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE 有权
公开(公告)号：US20210326204A1
公开(公告)日：2021-10-21
申请号：US17106663
申请日：2020-11-30
申请人： Rambus Inc.
发明人： Frederick A. WARE , Brent S. HAUKNESS , Lawrence LAI
IPC分类号： G06F11/10
摘要： A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

4. 发明申请

US20200212960A1 CONFIGURABLE, POWER SUPPLY VOLTAGE REFERENCED SINGLE-ENDED SIGNALING WITH ESD PROTECTION 审中-公开
公开(公告)号：US20200212960A1
公开(公告)日：2020-07-02
申请号：US16685861
申请日：2019-11-15
申请人： Rambus Inc.
发明人： John W. POULTON , Frederick A. WARE , Carl W. WERNER
IPC分类号： H04B3/56 , H04L25/02 , G06F13/40 , H03F3/24 , H04B3/54
摘要： A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

5. 发明申请

US20220343992A1 COMMAND/ADDRESS CHANNEL ERROR DETECTION 有权
公开(公告)号：US20220343992A1
公开(公告)日：2022-10-27
申请号：US17746674
申请日：2022-05-17
申请人： Rambus Inc.
发明人： John Eric LINSTADT , Frederick A. WARE
IPC分类号： G11C29/42 , G11C8/18 , G11C29/18 , G11C29/44
摘要： A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.

6. 发明申请

US20200073756A1 MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE 审中-公开
公开(公告)号：US20200073756A1
公开(公告)日：2020-03-05
申请号：US16565848
申请日：2019-09-10
申请人： Rambus Inc.
发明人： Frederick A. WARE , Brent S. HAUKNESS , Lawrence LAI
IPC分类号： G06F11/10
摘要： A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

7. 发明申请

US20160342487A1 HIGH PERFORMANCE PERSISTENT MEMORY 审中-公开
标题翻译：高性能的记忆
公开(公告)号：US20160342487A1
公开(公告)日：2016-11-24
申请号：US15114795
申请日：2014-12-19
申请人： RAMBUS INC.
发明人： Frederick A. WARE , J. James TRINGALI , Ely TSERN
IPC分类号： G06F11/14 , G06F3/06
CPC分类号： G06F11/1471 , G06F3/0619 , G06F3/0634 , G06F3/0647 , G06F3/0685 , G06F2201/805 , G06F2201/84 , G11C7/20 , G11C14/0018
摘要： The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.
摘要翻译：本文描述的实施例描述了在包括用于易失性存储器和非易失性存储器的两个或多个存储器技术的多层存储器系统中的非易失性存储器持久性的技术。

8. 发明申请

US20160314085A1 HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE 审中-公开
标题翻译：具有改进的指令地址和芯片选择信号模式的高容量存储器系统
公开(公告)号：US20160314085A1
公开(公告)日：2016-10-27
申请号：US15101870
申请日：2014-12-18
申请人： RAMBUS INC.
发明人： Frederick A. WARE , Abhijit ABHYANKAR , Suresh RAJAN
IPC分类号： G06F13/16 , G06F13/42
CPC分类号： G06F13/1673 , G06F13/4243
摘要： A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.
摘要翻译：存储器控制器和存储器模块中的缓冲器各自以两种模式运行，这取决于控制器和模块通过其连接的主板的类型。在第一模式中，控制器独立地向每个模块发送解码的芯片选择信号，并且主板数据信道使用到每个模块的多点连接。在第二模式中，母板具有到每个存储器模块的点对点数据信道和命令地址连接，并且控制器向每个模块发送完全编码的芯片选择信号组。缓冲器以模态方式进行操作，以根据模式正确选择每个事务的一个或多个模块上的存储器设备的等级或部分等级。

9. 发明申请

US20160217839A1 HIGH CAPACITY MEMORY SYSTEM 有权
标题翻译：高容量存储器系统
公开(公告)号：US20160217839A1
公开(公告)日：2016-07-28
申请号：US15024454
申请日：2014-09-24
申请人： RAMBUS INC.
发明人： Frederick A. WARE , Suresh RAJAN
IPC分类号： G11C7/10
CPC分类号： G11C7/1063 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1072 , G11C29/025 , G11C29/028
摘要： The embodiments described herein describe technologies for memory systems. One implementation of a memory module includes multiple device sites coupled to the a data query (DQ) buffer component via data lines and coupled to a command and address (CA) buffer component via chip select (CS) lines. A first number of the CS lines between the CA buffer component and any combination of two or more of the multiple device sites is greater than a second number of the CS lines between the CA buffer component and a single one of the multiple device sites.
摘要翻译：这里描述的实施例描述了用于存储器系统的技术。存储器模块的一个实现包括经由数据线耦合到数据查询（DQ）缓冲器组件的多个设备站点，并经由芯片选择（CS）线路耦合到命令和地址（CA）缓冲器组件。 CA缓冲器组件与多个设备站点中的两个或多个的任何组合之间的第一个CS行数大于CA缓冲器组件与多个设备站点中的单个站点之间的CS行的第二个数量。

10. 发明申请

US20210303383A1 MEMORY MODULE REGISTER ACCESS 有权
公开(公告)号：US20210303383A1
公开(公告)日：2021-09-30
申请号：US17236445
申请日：2021-04-21
申请人： Rambus Inc.
发明人： Thomas J. GIOVANNINI , Catherine CHEN , Scott C. BEST , John Eric LINSTADT , Frederick A. WARE
IPC分类号： G06F11/07 , G11C29/44 , G06F13/00 , G11C5/04 , G11C7/20 , G11C8/12 , G11C29/26
摘要： During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

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