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1. 发明授权

US11194509B2 High capacity, high performance memory system 有权
公开(公告)号：US11194509B2
公开(公告)日：2021-12-07
申请号：US15689173
申请日：2017-08-29
申请人： Rambus Inc.
发明人： Frederick Ware
IPC分类号： G06F3/06 , G06F12/06 , G06F13/40 , G06F13/16 , G06F13/42
摘要： Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

2. 发明申请

US20180074758A1 HIGH CAPACITY, HIGH PERFORMANCE MEMORY SYSTEM 审中-公开
公开(公告)号：US20180074758A1
公开(公告)日：2018-03-15
申请号：US15689173
申请日：2017-08-29
申请人： Rambus Inc.
发明人： Frederick Ware
IPC分类号： G06F3/06 , G06F12/06 , G06F13/16
CPC分类号： G06F3/0659 , G06F12/06 , G06F13/1684 , G06F13/1689 , G06F13/4086 , G06F13/4256
摘要： Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

3. 发明申请

US20150023118A1 RECONFIGURABLE MEMORY SYSTEM DATA STROBES 有权
标题翻译：可重构存储器系统数据条
公开(公告)号：US20150023118A1
公开(公告)日：2015-01-22
申请号：US14509572
申请日：2014-10-08
申请人： RAMBUS INC.
发明人： Ian Shaeffer , Frederick Ware , Craig E. Hampel
IPC分类号： G06F3/06 , G11C7/22
CPC分类号： G06F3/0634 , G06F3/0665 , G06F3/0689 , G06F13/1694 , G06F2212/262 , G11C7/22
摘要： In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of the components of the differential data strobe may be used as a timing reference for a first portion of the set of data signals and the other component used as a timing reference for a second portion of the set of data signals. Different data mask-related schemes also may be invoked for different modes of operation. For example, in a first mode of operation a memory controller may generate a data mask signal to prevent a portion of a set of data from being written to a memory array. Then, in a second mode of operation the memory controller may invoke a coded value replacement scheme or a data strobe transition inhibition scheme to prevent a portion of a set of data from being written to a memory array.
摘要翻译：在可重新配置的基于数据选通的存储器系统中，数据选通可以在不同的操作模式下重新安排。例如，在一种操作模式中，差分数据选通可以用作给定的一组数据信号的定时参考。在第二操作模式中，可以将差分数据选通的一个组件用作数据信号组的第一部分的定时参考，另一组件用作该组数据信号的第二部分的定时参考数据信号。也可以针对不同的操作模式调用不同的数据掩码相关方案。例如，在第一操作模式中，存储器控制器可以生成数据掩码信号以防止一组数据被写入存储器阵列。然后，在第二操作模式中，存储器控制器可以调用编码值替换方案或数据选通转换禁止方案，以防止一组数据被写入存储器阵列。

4. 发明授权

US12014089B2 High capacity, high performance memory system 有权
公开(公告)号：US12014089B2
公开(公告)日：2024-06-18
申请号：US18121231
申请日：2023-03-14
申请人： Rambus Inc.
发明人： Frederick Ware
IPC分类号： G06F3/06 , G06F12/06 , G06F13/16 , G06F13/40 , G06F13/42
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0683 , G06F12/06 , G06F13/1689 , G06F13/4086 , G06F13/4256 , G06F13/1684
摘要： Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

5. 发明授权

US11630607B2 High capacity, high performance memory system 有权
公开(公告)号：US11630607B2
公开(公告)日：2023-04-18
申请号：US17521399
申请日：2021-11-08
申请人： Rambus Inc.
发明人： Frederick Ware
IPC分类号： G06F3/06 , G06F12/06 , G06F13/40 , G06F13/16 , G06F13/42
摘要： Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

6. 发明申请

US20200059263A1 PSEUDO-DIFFERENTIAL SIGNALING FOR MODIFIED SINGLE-ENDED INTERFACE 审中-公开
公开(公告)号：US20200059263A1
公开(公告)日：2020-02-20
申请号：US16544475
申请日：2019-08-19
申请人： Rambus Inc.
发明人： Frederick Ware , Carl Werner
IPC分类号： H04B3/32
摘要： Disclosed is a signaling circuit. A switch circuit generates an internal reference supply voltage and an internal lower supply voltage, from first and second power supply voltages. A transmit circuit drives a high bit from the first power supply voltage, and drives a low bit from the internal lower supply voltage. The second terminal of the data output is connected to the internal reference supply voltage.

7. 发明授权

US11842762B2 System application of DRAM component with cache mode 有权
公开(公告)号：US11842762B2
公开(公告)日：2023-12-12
申请号：US17439215
申请日：2020-03-16
申请人： RAMBUS INC.
发明人： Frederick Ware , Thomas Vogelsang , Michael Raymond Miller , Collins Williams
IPC分类号： G11C11/4093 , G06F12/0895 , G11C8/18 , G11C11/4076 , G11C11/408
CPC分类号： G11C11/4093 , G06F12/0895 , G11C8/18 , G11C11/4076 , G11C11/4087 , G11C2207/2245
摘要： Disclosed is a memory system that has a memory controller and may have a memory component. The memory component may be a dynamic random access memory (DRAM). The memory controller is connectable to the memory component. The memory component has at least one data row and at least one tag row different from and associated with the at least one data row. The memory system is to implement a cache having multiple ways to hold a data group. The memory controller is operable in each of a plurality of operating modes. The operating modes include a first operating mode and a second operating mode. The first operating mode and the second operating mode have differing addressing and timing for accessing the data group. The memory controller has cache read logic that sends a cache read command, cache results logic that receives a response from the memory component, and cache fetch logic.

8. 发明申请

US20210067197A1 PSEUDO-DIFFERENTIAL SIGNALING FOR MODIFIED SINGLE-ENDED INTERFACE 有权
公开(公告)号：US20210067197A1
公开(公告)日：2021-03-04
申请号：US17023169
申请日：2020-09-16
申请人： Rambus Inc.
发明人： Frederick Ware , Carl Werner
IPC分类号： H04B3/32
摘要： Disclosed is a signaling circuit. A switch circuit generates an internal reference supply voltage and an internal lower supply voltage, from first and second power supply voltages. A transmit circuit drives a high bit from the first power supply voltage, and drives a low bit from the internal lower supply voltage. The second terminal of the data output is connected to the internal reference supply voltage.

9. 发明授权

US09703503B2 Reconfigurable memory system data strobes 有权
公开(公告)号：US09703503B2
公开(公告)日：2017-07-11
申请号：US14509572
申请日：2014-10-08
申请人： RAMBUS INC.
发明人： Ian Shaeffer , Frederick Ware , Craig E. Hampel
IPC分类号： G06F3/06 , G06F13/16 , G11C7/22
CPC分类号： G06F3/0634 , G06F3/0665 , G06F3/0689 , G06F13/1694 , G06F2212/262 , G11C7/22
摘要： In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of the components of the differential data strobe may be used as a timing reference for a first portion of the set of data signals and the other component used as a timing reference for a second portion of the set of data signals. Different data mask-related schemes also may be invoked for different modes of operation. For example, in a first mode of operation a memory controller may generate a data mask signal to prevent a portion of a set of data from being written to a memory array. Then, in a second mode of operation the memory controller may invoke a coded value replacement scheme or a data strobe transition inhibition scheme to prevent a portion of a set of data from being written to a memory array.

10. 发明申请

US20140068169A1 Independent Threading Of Memory Devices Disposed On Memory Modules 审中-公开
标题翻译：内存模块中的内存设备的独立线程
公开(公告)号：US20140068169A1
公开(公告)日：2014-03-06
申请号：US13923184
申请日：2013-06-20
申请人： Rambus Inc.
发明人： Frederick Ware , Craig E. Hampel , Ian Shaeffer , Scott C. Best
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G06F13/1684 , G06F13/4234 , G11C5/00
摘要： A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command.
摘要翻译：存储器模块包括其上具有信号线的衬底，其形成控制路径和多个数据路径。多个存储器件安装在基片上。每个存储器件耦合到控制路径和不同的数据路径。存储器模块包括控制电路，以使得每个存储器设备能够在一系列存储器访问命令中处理不同的相应存储器访问命令，并且响应于处理的存储器访问命令在不同的数据路径上输出数据。

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