专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07085274B1 Context-switched multi-stream pipelined reorder engine 有权
公开(公告)号：US07085274B1
公开(公告)日：2006-08-01
申请号：US09955122
申请日：2001-09-19
申请人： Rami Rahim , Venkateswarlu Talapaneni , Philippe G. Lacroute
发明人： Rami Rahim , Venkateswarlu Talapaneni , Philippe G. Lacroute
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L2012/565 , H04L2012/5681
摘要： A pipelined reorder engine reorders data items received over a network on a per-source basis. Context memories correspond to each of the possible sources. The pipeline includes a plurality of pipeline stages that together simultaneously operate on the data items. The context memories are operatively coupled to the pipeline stages and store information relating to a state of reordering for each of the sources. The pipeline stages read from and update the context memories based on the source of the data item being processed.

2. 发明授权

US08737403B2 Context-switched multi-stream pipelined reorder engine 有权
标题翻译：上下文交换多流流水线重排序引擎
公开(公告)号：US08737403B2
公开(公告)日：2014-05-27
申请号：US13329616
申请日：2011-12-19
申请人： Rami Rahim , Venkateswarlu Talapaneni , Philippe G. Lacroute
发明人： Rami Rahim , Venkateswarlu Talapaneni , Philippe G. Lacroute
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L2012/565 , H04L2012/5681
摘要： A pipelined reorder engine reorders data items received over a network on a per-source basis. Context memories correspond to each of the possible sources. The pipeline includes a plurality of pipeline stages that together simultaneously operate on the data items. The context memories are operatively coupled to the pipeline stages and store information relating to a state of reordering for each of the sources. The pipeline stages read from and update the context memories based on the source of the data item being processed.
摘要翻译：流水线重新排序引擎根据每个来源重新排序通过网络接收的数据项。上下文存储器对应于每个可能的源。流水线包括一起同时对数据项进行操作的多个流水线级。上下文存储器可操作地耦合到流水线级并且存储与每个源的重新排序状态有关的信息。流水线级基于正在处理的数据项的来源读取并更新上下文存储器。

3. 发明授权

US08102858B1 Context-switched multi-stream pipelined reorder engine 有权
标题翻译：上下文交换多流流水线重排序引擎
公开(公告)号：US08102858B1
公开(公告)日：2012-01-24
申请号：US12499543
申请日：2009-07-08
申请人： Rami Rahim , Venkateswarlu Talapaneni , Philippe G Lacroute
发明人： Rami Rahim , Venkateswarlu Talapaneni , Philippe G Lacroute
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L2012/565 , H04L2012/5681
摘要： A pipelined reorder engine reorders data items received over a network on a per-source basis. Context memories correspond to each of the possible sources. The pipeline includes a plurality of pipeline stages that together simultaneously operate on the data items. The context memories are operatively coupled to the pipeline stages and store information relating to a state of reordering for each of the sources. The pipeline stages read from and update the context memories based on the source of the data item being processed.
摘要翻译：流水线重新排序引擎根据每个来源重新排序通过网络接收的数据项。上下文存储器对应于每个可能的源。流水线包括一起同时对数据项进行操作的多个流水线级。上下文存储器可操作地耦合到流水线级并且存储与每个源的重新排序状态有关的信息。流水线级基于正在处理的数据项的来源读取并更新上下文存储器。

4. 发明授权

US07577149B1 Context-switched multi-stream pipelined reorder engine 有权
标题翻译：上下文交换多流流水线重排序引擎
公开(公告)号：US07577149B1
公开(公告)日：2009-08-18
申请号：US11424145
申请日：2006-06-14
申请人： Rami Rahim , Venkateswarlu Talapaneni , Philippe G. LaCroute
发明人： Rami Rahim , Venkateswarlu Talapaneni , Philippe G. LaCroute
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L2012/565 , H04L2012/5681
摘要： A pipelined reorder engine reorders data items received over a network on a per-source basis. Context memories correspond to each of the possible sources. The pipeline includes a plurality of pipeline stages that together simultaneously operate on the data items. The context memories are operatively coupled to the pipeline stages and store information relating to a state of reordering for each of the sources. The pipeline stages read from and update the context memories based on the source of the data item being processed.
摘要翻译：流水线重新排序引擎根据每个来源重新排序通过网络接收的数据项。上下文存储器对应于每个可能的源。流水线包括一起同时对数据项进行操作的多个流水线级。上下文存储器可操作地耦合到流水线级并且存储与每个源的重新排序状态有关的信息。流水线级基于正在处理的数据项的来源读取并更新上下文存储器。

5. 发明授权

US07039774B1 Memory allocation using a memory address pool 失效
标题翻译：使用内存地址池进行内存分配
公开(公告)号：US07039774B1
公开(公告)日：2006-05-02
申请号：US10062424
申请日：2002-02-05
申请人： Jorge Cruz-Rios , Rami Rahim , Venkateswarlu Talapaneni , Pradeep Sindhu
发明人： Jorge Cruz-Rios , Rami Rahim , Venkateswarlu Talapaneni , Pradeep Sindhu
IPC分类号： G06F12/00
CPC分类号： G06F12/023
摘要： A system for managing memory includes a memory and a memory allocation unit. The memory stores a pool of memory addresses for writing data to the memory and stores a counter value. The memory allocation unit retrieves memory addresses from the pool in response to write requests from data sources. The memory allocation unit further replenishes the memory addresses in the pool when the pool is emptied and increments the counter value in response to each replenishment of the memory addresses in the pool.
摘要翻译：用于管理存储器的系统包括存储器和存储器分配单元。存储器存储用于将数据写入存储器的存储器地址池并存储计数器值。内存分配单元响应于来自数据源的写入请求从池中检索存储器地址。当池被清空时，存储器分配单元进一步补充池中的存储器地址，并响应于池中的存储器地址的每次补充递增计数器值。

6. 发明授权

US07171530B1 Memory allocation using a memory address pool 失效
标题翻译：使用内存地址池进行内存分配
公开(公告)号：US07171530B1
公开(公告)日：2007-01-30
申请号：US11366386
申请日：2006-03-03
申请人： Jorge Cruz-Rios , Rami Rahim , Venkateswarlu Talapaneni , Pradeep Sindhu
发明人： Jorge Cruz-Rios , Rami Rahim , Venkateswarlu Talapaneni , Pradeep Sindhu
IPC分类号： G06F12/00
CPC分类号： G06F12/023
摘要： A system maintains a first counter value that indicates a number of times memory addresses in a memory address pool have been replenished. The system further maintains a second counter value that indicates a number of times a circular buffer has been filled with memory addresses retrieved from the memory address pool. The system ages memory addresses allocated to memory write requests based on the first and second counter values.
摘要翻译：系统维护指示存储器地址池中的存储器地址已经被补充的次数的第一计数器值。系统进一步维护第二计数器值，其指示循环缓冲器已经被从存储器地址池检索的存储器地址填充的次数。系统基于第一和第二计数器值来分配分配给存储器写入请求的存储器地址。

7. 发明授权

US07406089B1 Data verification using signature 有权
标题翻译：使用签名数据验证
公开(公告)号：US07406089B1
公开(公告)日：2008-07-29
申请号：US10210511
申请日：2002-07-31
申请人： Rami Rahim , Pradeep Sindhu
发明人： Rami Rahim , Pradeep Sindhu
IPC分类号： H04L9/30
CPC分类号： H04L63/123
摘要： A system processes packets in a network device and includes a memory for buffering the packets. The memory may store the packets in memory in data cells. To expedite packet processing, portions of the packet are extracted and placed in a notification, which is then used for packet processing operations, such as route lookup, policing, and accounting. The notification may also include address elements, such as address offsets, that define the locations of the data cells in memory. The address elements can be used to read the data cells from the memory when packet processing is done. If the notification cannot hold all the address elements, additional cells, indirect cells, are created for holding the remaining address elements. The indirect cells are formed in a linked list. The notification contains an address element. To prevent reading incorrect indirect cells, each indirect cell is written with a signature that is created based on the notification. When an indirect cell is read out, the signature is checked to determine whether it belongs to that notification. If the signature is not correct, this may mean that the indirect cell has not yet been written to memory, or that the indirect cell was in some way corrupted during writing, storing, or reading.
摘要翻译：系统处理网络设备中的分组，并且包括用于缓冲分组的存储器。存储器可以将数据包存储在数据单元中。为了加快分组处理，分组的部分被提取并放置在通知中，然后用于诸如路由查找，管理和计费之类的分组处理操作。通知还可以包括定义存储器中的数据单元的位置的地址元素，例如地址偏移。当数据包处理完成时，地址元素可用于从存储器读取数据单元。如果通知不能容纳所有地址元素，则创建附加单元格，间接单元格以保留剩余的地址单元。间接细胞在链表中形成。通知包含地址元素。为了防止读取不正确的间接单元格，每个间接单元都将使用基于通知创建的签名进行写入。当读取间接单元时，检查签名以确定它是否属于该通知。如果签名不正确，这可能意味着间接单元格尚未写入存储器，或间接单元格在写入，存储或读取期间以某种方式损坏。

8. 发明授权

US07613192B1 Reorder engine with error recovery 有权
标题翻译：重新排序引擎与错误恢复
公开(公告)号：US07613192B1
公开(公告)日：2009-11-03
申请号：US11684394
申请日：2007-03-09
申请人： Rami Rahim
发明人： Rami Rahim
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/283 , H04L47/32 , H04L47/34 , H04L49/90 , H04L49/9094
摘要： A reorder engine classifies information relating to incoming data items as belonging to either a first, second, or third region. The information relating to the data items may arrive at the reorder engine out of order. The data items each include a sequence number through which the reorder engine may reconstruct the correct order of the data items. Based on the classification, the reorder engine may either process the data items normally or drop certain ones of the data items. The majority of incoming data items will fall in the first region and are processed normally. Data items arriving in the second region indicate that a previous data item is late or delayed. If this previous data item is delayed but does eventually arrive, it will arrive in the third region and is simply ignored.
摘要翻译：重新排序引擎将与进入数据项相关的信息归类为属于第一，第二或第三区域。与数据项相关的信息可能无法到达重新排序引擎。数据项每个都包括序列号，重新排序引擎可以通过该序列号重建数据项的正确顺序。基于分类，重新排序引擎可以正常处理数据项或者丢弃某些数据项。大部分传入的数据项将落在第一个区域并被正常处理。到达第二区域的数据项表示先前的数据项被延迟或延迟。如果此前的数据项目延迟但最终到达，则它将到达第三个区域，并被忽略。

9. 发明授权

US07554919B1 Systems and methods for improving packet scheduling accuracy 有权
标题翻译：提高数据包调度精度的系统和方法
公开(公告)号：US07554919B1
公开(公告)日：2009-06-30
申请号：US10863772
申请日：2004-06-09
申请人： Sreeram Veeragandham , Rami Rahim , Song Zhang , Anurag P. Gupta , Jorge Cruz-Rios , Jayabharat Boddu , Jeffrey R. Zimmer , Jia-Chang Wang , Srihari Shoroff , Chi-Chung K. Chen
发明人： Sreeram Veeragandham , Rami Rahim , Song Zhang , Anurag P. Gupta , Jorge Cruz-Rios , Jayabharat Boddu , Jeffrey R. Zimmer , Jia-Chang Wang , Srihari Shoroff , Chi-Chung K. Chen
IPC分类号： H04J1/16 , H04J3/14 , H04J3/16 , H04J3/22
CPC分类号： H04L47/623 , H04L47/263 , H04L47/50 , H04L47/522 , H04L47/6265
摘要： A packet scheduler is configured to perform quality of service (QoS) scheduling on a per-data unit basis. A downstream processing engine is operatively connected to the packet scheduler for receiving forwarded packets. A feedback path is operatively connected between the downstream processing engine and the packet scheduler for transmitting a net data unit change value reflecting a change in packet size between an output of the packet scheduler and an output of the downstream processing engine.
摘要翻译：分组调度器被配置为在每个数据单元的基础上执行服务质量（QoS）调度。下游处理引擎可操作地连接到分组调度器以接收转发的分组。反馈路径可操作地连接在下游处理引擎和分组调度器之间，用于发送反映分组调度器的输出和下游处理引擎的输出之间的分组大小变化的净数据单元变化值。

10. 发明授权

US07209482B1 Reorder engine with error recovery 有权
标题翻译：重新排序引擎与错误恢复
公开(公告)号：US07209482B1
公开(公告)日：2007-04-24
申请号：US10024553
申请日：2001-12-21
申请人： Rami Rahim
发明人： Rami Rahim
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/283 , H04L47/32 , H04L47/34 , H04L49/90 , H04L49/9094
摘要： A reorder engine classifies information relating to incoming data items as belonging to either a first, second, or third region. The information relating to the data items may arrive at the reorder engine out of order. The data items each include a sequence number through which the reorder engine may reconstruct the correct order of the data items. Based on the classification, the reorder engine may either process the data items normally or drop certain ones of the data items. The majority of incoming data items will fall in the first region and are processed normally. Data items arriving in the second region indicate that a previous data item is late or delayed. If this previous data item is delayed but does eventually arrive, it will arrive in the third region and is simply ignored.
摘要翻译：重新排序引擎将与进入的数据项相关的信息归类为属于第一，第二或第三区域。与数据项相关的信息可能无法到达重新排序引擎。数据项每个都包括序列号，重新排序引擎可以通过该序列号重建数据项的正确顺序。基于分类，重新排序引擎可以正常处理数据项或者丢弃某些数据项。大部分传入的数据项将落在第一个区域并被正常处理。到达第二区域的数据项表示先前的数据项被延迟或延迟。如果此前的数据项目延迟但最终到达，则它将到达第三个区域，并被忽略。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式