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1. 发明授权

US08165301B1 Input-output device and storage controller handshake protocol using key exchange for data security 有权
标题翻译：输入输出设备和存储控制器握手协议，使用密钥交换进行数据安全
公开(公告)号：US08165301B1
公开(公告)日：2012-04-24
申请号：US11398321
申请日：2006-04-04
申请人： Rey Bruce , Marizonne Operio Fuentes , Raquel Bautista David
发明人： Rey Bruce , Marizonne Operio Fuentes , Raquel Bautista David
IPC分类号： H04L9/06
CPC分类号： H04L9/0894 , G06F21/82 , H04L9/0822
摘要： A protocol for providing secured IO device and storage controller handshake protocol; IO device controlled cipher settings, and secured data storage and access in memory. An IO device requesting data transfer with encryption and/or decryption, requests session keys from the processor. The processor generates a fresh public-private key pair for the session. The public key is sent to the requesting IO device; the private key is momentarily saved by the processor for the session. The requesting IO device generates a secret key and its desired cipher setting; furthermore, encrypts the secret key and cipher setting using the public key, and sends secret key and cipher setting to the processor. The processor uses the private key to decrypt the secret key and cipher setting. The cipher setting is used for configuring the data processing core. The secret key is used for encryption and/or decryption of the data being transferred. All keys are not permanently saved.
摘要翻译：用于提供安全的IO设备和存储控制器握手协议的协议; IO设备控制密码设置，以及安全的数据存储和内存访问。通过加密和/或解密请求数据传输的IO设备从处理器请求会话密钥。处理器为会话生成一个新的公私密钥对。公钥被发送到请求的IO设备; 私钥由处理器暂时保存用于会话。请求的IO设备生成秘密密钥及其期望的密码设置; 此外，使用公钥加密秘密密钥和密码设置，并向处理器发送秘密密钥和密码设置。处理器使用私钥来解密密钥和密码设置。密码设置用于配置数据处理核心。秘密密钥用于对正在传送的数据进行加密和/或解密。所有键都不会永久保存。

2. 发明授权

US09400617B2 Hardware-assisted DMA transfer with dependency table configured to permit-in parallel-data drain from cache without processor intervention when filled or drained 有权
标题翻译：硬件辅助DMA传输与依赖表配置为允许并行数据从高速缓存中排出，而无需处理器干预时，填充或排出
公开(公告)号：US09400617B2
公开(公告)日：2016-07-26
申请号：US14217467
申请日：2014-03-17
申请人： Cyrill Ponce , Marizonne Operio Fuentes , Gianico Geonzon Noble
发明人： Cyrill Ponce , Marizonne Operio Fuentes , Gianico Geonzon Noble
IPC分类号： G06F3/00 , G06F3/06 , G06F12/08
CPC分类号： G06F12/1081 , G06F3/061 , G06F3/0656 , G06F3/0683 , G06F12/08 , G06F12/0875 , G06F13/1673 , G06F13/28 , G06F2212/452 , G11C7/1072
摘要： The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core's descriptors1 are correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. 1 Descriptors are set of instructions that is used to activate the DMA controller.By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.
摘要翻译：本发明提供了源（闪存/ IO）和目的地（IO /闪存）核之间的数据流通信控制。源和目标内核同时启动而不是串行启动，并从处理器提供和设置的描述符获取指令。每个源和目标核心的描述符1通过向硬件辅助机制提供信息由处理器相互关联或相互关联。硬件辅助机制负责调节从源到目的地的数据传输。流量跟踪器保证目的地所需的数据存在。 1描述符是用于激活DMA控制器的指令集。通过将本发明应用于先前的方法/解决方案，闪存和IO总线之间的数据等待时间将会降低。闪存和IO总线之间的数据传输正在进行时，处理器中断将被最小化。

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