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1. 发明授权

US08165301B1 Input-output device and storage controller handshake protocol using key exchange for data security 有权
标题翻译：输入输出设备和存储控制器握手协议，使用密钥交换进行数据安全
公开(公告)号：US08165301B1
公开(公告)日：2012-04-24
申请号：US11398321
申请日：2006-04-04
申请人： Rey Bruce , Marizonne Operio Fuentes , Raquel Bautista David
发明人： Rey Bruce , Marizonne Operio Fuentes , Raquel Bautista David
IPC分类号： H04L9/06
CPC分类号： H04L9/0894 , G06F21/82 , H04L9/0822
摘要： A protocol for providing secured IO device and storage controller handshake protocol; IO device controlled cipher settings, and secured data storage and access in memory. An IO device requesting data transfer with encryption and/or decryption, requests session keys from the processor. The processor generates a fresh public-private key pair for the session. The public key is sent to the requesting IO device; the private key is momentarily saved by the processor for the session. The requesting IO device generates a secret key and its desired cipher setting; furthermore, encrypts the secret key and cipher setting using the public key, and sends secret key and cipher setting to the processor. The processor uses the private key to decrypt the secret key and cipher setting. The cipher setting is used for configuring the data processing core. The secret key is used for encryption and/or decryption of the data being transferred. All keys are not permanently saved.
摘要翻译：用于提供安全的IO设备和存储控制器握手协议的协议; IO设备控制密码设置，以及安全的数据存储和内存访问。通过加密和/或解密请求数据传输的IO设备从处理器请求会话密钥。处理器为会话生成一个新的公私密钥对。公钥被发送到请求的IO设备; 私钥由处理器暂时保存用于会话。请求的IO设备生成秘密密钥及其期望的密码设置; 此外，使用公钥加密秘密密钥和密码设置，并向处理器发送秘密密钥和密码设置。处理器使用私钥来解密密钥和密码设置。密码设置用于配置数据处理核心。秘密密钥用于对正在传送的数据进行加密和/或解密。所有键都不会永久保存。

2. 发明授权

US07716389B1 Direct memory access controller with encryption and decryption for non-blocking high bandwidth I/O transactions 有权
标题翻译：直接存储器访问控制器，具有用于非阻塞高带宽I / O事务的加密和解密
公开(公告)号：US07716389B1
公开(公告)日：2010-05-11
申请号：US11378762
申请日：2006-03-17
申请人： Rey Bruce , Raquel Bautista David , Shielou Vicencio Estrada
发明人： Rey Bruce , Raquel Bautista David , Shielou Vicencio Estrada
IPC分类号： G06F3/00 , G06F13/00 , H04Q7/24 , H04L12/28
CPC分类号： G06F13/28
摘要： Due to the integration of multiple I/O device controllers in a storage controller and the need to provide secure and fast data transfers between the I/O devices and the storage controller, an architecture that can perform multiple encrypt/decrypt operations simultaneously is therefore needed to service multiple transfer requests without a negative impact on the speed of transfer and processing. The present invention relates to enhancing Direct Memory Access (DMA) operations between multiple IO devices and a storage controller by adding a Data Processing Core. Exemplary implementations are provided to illustrate the background mechanism used by a DMA controller that minimizes central-processing-unit (CPU) intervention and the multi-channel architecture which allows multiple IO requests to be serviced simultaneously.
摘要翻译：由于在存储控制器中集成了多个I / O设备控制器，并且需要在I / O设备和存储控制器之间提供安全和快速的数据传输，因此需要同时执行多个加密/解密操作的体系结构以服务多个传输请求，而不会对传输和处理的速度产生负面影响。本发明涉及通过添加数据处理核心来增强多个IO设备与存储控制器之间的直接存储器访问（DMA）操作。提供了示例性实现来说明DMA控制器使用的中央处理单元（CPU）干预最小化的背景机制以及允许同时对多个IO请求进行服务的多通道架构。

3. 发明申请

US20070158808A1 Multiple chip module and package stacking method for storage devices 有权
标题翻译：用于存储设备的多芯片模块和封装堆叠方法
公开(公告)号：US20070158808A1
公开(公告)日：2007-07-12
申请号：US11322442
申请日：2005-12-29
申请人： Rey Bruce , Ricardo Bruce , Patrick Bugayong , Joel Baylon
发明人： Rey Bruce , Ricardo Bruce , Patrick Bugayong , Joel Baylon
IPC分类号： H01L23/02
CPC分类号： H01L25/105 , H01L24/16 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/01079 , H01L2924/15331 , H01L2924/1627
摘要： Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. Combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.
摘要翻译：堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。这些模块和裸片在基板中的组合产生具有特定功能或一定范围的存储容量的封装。使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。可以在垂直和水平方向进行扩展。

4. 发明授权

US07826243B2 Multiple chip module and package stacking for storage devices 有权
标题翻译：用于存储设备的多芯片模块和封装堆叠
公开(公告)号：US07826243B2
公开(公告)日：2010-11-02
申请号：US11322442
申请日：2005-12-29
申请人： Rey Bruce , Ricardo Bruce , Patrick Digamon Bugayong , Joel Alonzo Baylon
发明人： Rey Bruce , Ricardo Bruce , Patrick Digamon Bugayong , Joel Alonzo Baylon
IPC分类号： G11C5/02
CPC分类号： H01L25/105 , H01L24/16 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/01079 , H01L2924/15331 , H01L2924/1627
摘要： Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.
摘要翻译：堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。可以在垂直和水平方向进行扩展。

5. 发明申请

US20210357119A1 ARTIFICIAL INTELLIGENCE-BASED HYBRID RAID CONTROLLER DEVICE 有权
公开(公告)号：US20210357119A1
公开(公告)日：2021-11-18
申请号：US17322822
申请日：2021-05-17
申请人： Rey Bruce , Ricky Bruce , Lawrence Salazar , Noeme Salazar , Julian Bruce
发明人： Rey Bruce , Ricky Bruce , Lawrence Salazar , Noeme Salazar , Julian Bruce
IPC分类号： G06F3/06 , G06N3/063
摘要： The present disclosure provides an artificial intelligence-based hybrid RAID controller device. The artificial intelligence-based hybrid RAID controller device includes CPU to execute instructions to run overall operation of the artificial intelligence-based hybrid RAID controller device. In addition, the artificial intelligence-based hybrid RAID controller device includes XOR/Cipher engine module to perform encryption and decryption to provide data security. Further, the artificial intelligence-based hybrid RAID controller device includes DSP module to perform pre-processing of data for an artificial intelligence inference engine module. Furthermore, the artificial intelligence inference engine module facilitates the artificial intelligence-based hybrid RAID controller device to perform in-storage processing. Moreover, the artificial intelligence-based hybrid RAID controller device includes a plurality of PCIe controller connected to an array of SSDs. The XOR/Cipher engine module embeds XOR engines to perform RAID parity computation to provide data redundancy.

6. 发明申请

US20070288692A1 Hybrid Multi-Tiered Caching Storage System 有权
标题翻译：混合多层缓存存储系统
公开(公告)号：US20070288692A1
公开(公告)日：2007-12-13
申请号：US11450023
申请日：2006-06-08
申请人： Rey Bruce , Noeme Mateo , Ricky Nite
发明人： Rey Bruce , Noeme Mateo , Ricky Nite
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/28 , G06F3/061 , G06F3/064 , G06F3/0685 , G06F12/0866 , G06F12/0897 , G06F2212/2022 , G06F2212/217
摘要： A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution.
摘要翻译：描述了包括机械盘驱动装置，闪存装置，SDRAM存储装置和SRAM存储装置的混合存储系统。 IO处理器装置和DMA控制器装置被设计为消除主机干预。多层缓存系统和用于将逻辑地址映射到物理地址的新颖数据结构导致可配置和可扩展的高性能计算机数据存储解决方案。

7. 发明授权

US07620748B1 Hardware assisted non-volatile memory-to-input/output direct memory access (DMA) transfer 失效
标题翻译：硬件辅助非易失性存储器到输入/输出直接存储器访问（DMA）传输
公开(公告)号：US07620748B1
公开(公告)日：2009-11-17
申请号：US11399736
申请日：2006-04-06
申请人： Ricardo Bruce , Rey Bruce , Federico Zalzos Sambilay, Jr. , Bernard Sherwin Leung Chiw
发明人： Ricardo Bruce , Rey Bruce , Federico Zalzos Sambilay, Jr. , Bernard Sherwin Leung Chiw
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： In conventional storage device system, data transfer from memory to IO bus has to go through an intermediate volatile memory (cache). Data transfer therefore is completed in two steps—data is transferred from memory to cache and then from cache to the IO bus. Memory-to-cache transfer is handled by one DMA engine and another DMA engine for cache-to-IO transfer. To start the transfer, processor prepares the DMA transfer from memory to cache. Upon completion of the memory-to-cache transfer, the processor is interrupted to prepare the transfer from cache to IO. In between transfers, the processor has to intervene to setup the next transfer utilizing the precious processor cycles. The present invention improves on the above process using two novel schemes; 1) The use of dependency table to facilitate the transfer from memory-to-IO with less intervention from the processor and 2) the use of Bus Snooping scheme to bypass the transfer to cache making the transfer directly from memory to IO bus. This makes the transfer from memory to IO completed in single transfer.
摘要翻译：在传统的存储设备系统中，从存储器到IO总线的数据传输必须经过中间的易失性存储器（cache）。因此，数据传输在两个步骤中完成 - 数据从存储器传输到缓存，然后从缓存传输到IO总线。内存到高速缓存传输由一个DMA引擎和另一个DMA引擎来处理，用于缓存到IO传输。为了开始传输，处理器准备从存储器到缓存的DMA传输。在内存到高速缓存传输完成后，处理器被中断以准备从缓存到IO的传输。在传输之间，处理器必须介入以利用宝贵的处理器周期设置下一个传输。本发明使用两种新颖的方案改进了上述过程; 1）使用依赖关系表，以便从处理器的干预更少，从内存到IO的传输，以及2）使用总线侦听方案绕过传输缓存，从而将传输直接从内存传输到IO总线。这使得从内存到IO的传输在单次传输中完成。

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