专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08413029B2 Error correction capability adjustment of LDPC codes for storage device testing 失效
标题翻译：用于存储设备测试的LDPC码的纠错能力调整
公开(公告)号：US08413029B2
公开(公告)日：2013-04-02
申请号：US12402359
申请日：2009-03-11
申请人： Richard Rauschmayer , Hongwei Song
发明人： Richard Rauschmayer , Hongwei Song
IPC分类号： H03M13/03 , G11C29/00
CPC分类号： G11B20/1803 , G11B20/1816 , G11C29/028 , G11C29/42 , G11C2029/0411 , H03M13/1102
摘要： Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.
摘要翻译：本文描述的方法和结构提供了用于调整LDPC纠错码的纠错能力。例如，一个实施例的系统包括适于对已经用LDPC纠错码编码的数据进行解码的解码器。该系统还包括通信地耦合到解码器并且适于在解码器解码之前估计数据中的位值的检测器。检测器还适于基于比特值估计改变比特值，以减少LDPC纠错码的纠错能力。误差校正能力的降低是可调节的，从而可以逐渐分析存储设备的扇区故障率。

2. 发明申请

US20100185906A1 ERROR CORRECTION CAPABILITY ADJUSTMENT OF LDPC CODES FOR STORAGE DEVICE TESTING 失效
标题翻译：用于存储器件测试的LDPC码的错误校正能力调整
公开(公告)号：US20100185906A1
公开(公告)日：2010-07-22
申请号：US12402359
申请日：2009-03-11
申请人： Richard Rauschmayer , Hongwei Song
发明人： Richard Rauschmayer , Hongwei Song
IPC分类号： G11C29/04 , H03M13/35 , G06F11/10 , G06F11/22
CPC分类号： G11B20/1803 , G11B20/1816 , G11C29/028 , G11C29/42 , G11C2029/0411 , H03M13/1102
摘要： Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.
摘要翻译：本文描述的方法和结构提供了用于调整LDPC纠错码的纠错能力。例如，一个实施例的系统包括适于对已经用LDPC纠错码编码的数据进行解码的解码器。该系统还包括通信地耦合到解码器并且适于在解码器解码之前估计数据中的位值的检测器。检测器还适于基于比特值估计改变比特值，以减少LDPC纠错码的纠错能力。误差校正能力的降低是可调节的，从而可以逐渐分析存储设备的扇区故障率。

3. 发明授权

US08176400B2 Systems and methods for enhanced flaw scan in a data processing device 有权
标题翻译：用于在数据处理设备中增强缺陷扫描的系统和方法
公开(公告)号：US08176400B2
公开(公告)日：2012-05-08
申请号：US12556180
申请日：2009-09-09
申请人： Weijun Tan , Shaohua Yang , Hongwei Song , Richard Rauschmayer
发明人： Weijun Tan , Shaohua Yang , Hongwei Song , Richard Rauschmayer
IPC分类号： H03M13/00
CPC分类号： H04L1/0057 , H04L1/0045
摘要： Various embodiments of the present invention provide systems and methods for flaw scan in a data processing system. As one example, a data processing system is disclosed that includes a data detector circuit, a bit sign inverting circuit, and an LDPC decoder circuit. The data detector circuit receives a verification data set that is an invalid LDPC codeword, and applies a data detection algorithm to the verification data set to yield a detected output. The bit sign inverting circuit modifies the sign of one or more elements of a first derivative of the detected output to yield a second derivative of the detected output. The second derivative of the detected output is an expected valid LDPC codeword. The LDPC decoder circuit applies a decoding algorithm to the second derivative of the detected output to yield a decoded output.
摘要翻译：本发明的各种实施例提供了在数据处理系统中的缺陷扫描的系统和方法。作为一个示例，公开了包括数据检测器电路，位符号反相电路和LDPC解码器电路的数据处理系统。数据检测器电路接收作为无效LDPC码字的验证数据集，并将数据检测算法应用于验证数据集以产生检测到的输出。位符号反相电路修改检测输出的一阶导数的一个或多个元素的符号，以产生检测到的输出的二阶导数。所检测的输出的二阶导数是期望的有效LDPC码字。 LDPC解码器电路将解码算法应用于检测输出的二阶导数，以产生解码输出。

4. 发明授权

US07102549B1 Method and apparatus for programmable codeword encoding and decoding using truncated codewords 有权
标题翻译：用于使用截断码字进行可编码码字编码和解码的方法和装置
公开(公告)号：US07102549B1
公开(公告)日：2006-09-05
申请号：US11095766
申请日：2005-03-31
申请人： Zachary Keirn , Richard Rauschmayer , Hongwei Song , Peter D. Stroud , Fan Zhou
发明人： Zachary Keirn , Richard Rauschmayer , Hongwei Song , Peter D. Stroud , Fan Zhou
IPC分类号： H03M7/46
CPC分类号： H03M13/2906 , H03M13/618
摘要： Methods and apparatus are provided for programmable codeword encoding and decoding. Data blocks are represented as a number of codewords. Data is encoded into one or more full size codewords and at least one truncated codewords. Typically, data is encoded and decoded using one or more full size codewords and one truncated codeword. The truncated codewords are a two-dimensional array having a number of columns (or rows or both) less than the full size codeword. In this manner, the disclosed truncated codewords are adaptable to various system parameters that affect code rate.
摘要翻译：为可编程码字编码和解码提供了方法和装置。数据块被表示为多个码字。数据被编码成一个或多个全尺寸码字和至少一个截短码字。通常，使用一个或多个全尺寸码字和一个截短码字对数据进行编码和解码。截短的码字是具有小于全尺寸码字的列数（或行或两者）的二维阵列。以这种方式，所公开的截断的码字适用于影响码率的各种系统参数。

5. 发明申请

US20110080211A1 Systems and Methods for Noise Reduced Data Detection 审中-公开
标题翻译：降噪数据检测系统和方法
公开(公告)号：US20110080211A1
公开(公告)日：2011-04-07
申请号：US12992948
申请日：2009-04-17
申请人： Shaohua Yang , Yuan Xing Lee , Richard Rauschmayer , Hongwei Song , Jingfeng Liu , Weijun Tan
发明人： Shaohua Yang , Yuan Xing Lee , Richard Rauschmayer , Hongwei Song , Jingfeng Liu , Weijun Tan
IPC分类号： H03K5/00
CPC分类号： G11B20/24 , G11B20/10037 , G11B20/10194 , G11B20/10527 , G11B20/1833 , G11B20/1879 , G11B2020/1062 , G11B2020/10685 , G11B2020/10694 , G11B2020/10759 , G11B2020/183 , G11B2020/185 , G11B2220/2516 , H03M13/1105 , H03M13/2948 , H03M13/3746 , H03M13/6343 , H04L1/005 , H04L1/0057
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide noise reduced data processing circuits. Such circuits include a selector circuit, a sample set averaging circuit, and a data detection circuit. The selector circuit provides either a new sample set or an averaged sample set as a sample output based on a select control signal. The sample set averaging circuit receives the new sample set and provides the averaged sample set. The averaged sample set is based upon two or more instances of the new sample set. The data detection circuit receives the sample output, and performs a data detection algorithm on the sample output and provides the select control signal and a data output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，本发明的一些实施例提供降噪数据处理电路。这种电路包括选择器电路，采样组平均电路和数据检测电路。选择器电路基于选择控制信号提供新的采样集或平均采样集作为采样输出。样本集平均电路接收新的样本集并提供平均的样本集。平均采样集基于新样本集的两个或多个实例。数据检测电路接收采样输出，对采样输出执行数据检测算法，提供选择控制信号和数据输出。

6. 发明申请

US20110058631A1 Systems and Methods for Enhanced Flaw Scan in a Data Processing Device 有权
标题翻译：数据处理设备中增强型扫描扫描的系统和方法
公开(公告)号：US20110058631A1
公开(公告)日：2011-03-10
申请号：US12556180
申请日：2009-09-09
申请人： Weijun Tan , Shaohua Yang , Hongwei Song , Richard Rauschmayer
发明人： Weijun Tan , Shaohua Yang , Hongwei Song , Richard Rauschmayer
IPC分类号： H04L27/00
CPC分类号： H04L1/0057 , H04L1/0045
摘要： Various embodiments of the present invention provide systems and methods for flaw scan in a data processing system. As one example, a data processing system is disclosed that includes a data detector circuit, a bit sign inverting circuit, and an LDPC decoder circuit. The data detector circuit receives a verification data set that is an invalid LDPC codeword, and applies a data detection algorithm to the verification data set to yield a detected output. The bit sign inverting circuit modifies the sign of one or more elements of a first derivative of the detected output to yield a second derivative of the detected output. The second derivative of the detected output is an expected valid LDPC codeword. The LDPC decoder circuit applies a decoding algorithm to the second derivative of the detected output to yield a decoded output.
摘要翻译：本发明的各种实施例提供了在数据处理系统中的缺陷扫描的系统和方法。作为一个示例，公开了包括数据检测器电路，位符号反相电路和LDPC解码器电路的数据处理系统。数据检测器电路接收作为无效LDPC码字的验证数据集，并将数据检测算法应用于验证数据集以产生检测到的输出。位符号反相电路修改检测输出的一阶导数的一个或多个元素的符号，以产生检测到的输出的二阶导数。所检测的输出的二阶导数是期望的有效LDPC码字。 LDPC解码器电路将解码算法应用于检测输出的二阶导数，以产生解码输出。

7. 发明申请

US20090161245A1 Frequency Domain Approach for Efficient Computation of Fixed-point Equalization Targets 有权
标题翻译：用于有效计算定点均衡目标的频域方法
公开(公告)号：US20090161245A1
公开(公告)日：2009-06-25
申请号：US12273265
申请日：2008-11-18
申请人： George Mathew , Yuan Xing Lee , Hongwei Song , Richard Rauschmayer
发明人： George Mathew , Yuan Xing Lee , Hongwei Song , Richard Rauschmayer
IPC分类号： G11B5/035
CPC分类号： G11B20/10212 , G11B20/10046 , G11B20/10194 , G11B20/24 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for equalizing an input signal. For example, various embodiments of the present invention provide a method for performing equalization in a storage device. Such methods include providing an equalizer circuit that is governed by a target value, and a filter circuit that is governed by a filter coefficient. An initial value is provided to the equalizer circuit as the target value, and an overall target based at least in part on the initial value and the filter coefficient is calculated. An updated value is calculated based on the overall target, and the updated value is provided to the equalizer circuit as the target value.
摘要翻译：本发明的各种实施例提供了用于均衡输入信号的系统和方法。例如，本发明的各种实施例提供了一种用于在存储设备中执行均衡的方法。这样的方法包括提供由目标值控制的均衡器电路和由滤波器系数控制的滤波器电路。将初始值作为目标值提供给均衡器电路，并且至少部分地基于初始值和滤波器系数来计算总体目标。基于总体目标计算更新的值，并且将更新的值作为目标值提供给均衡器电路。

8. 发明授权

US07948699B2 Systems and methods for equalizer optimization in a storage access retry 有权
标题翻译：存储访问重试中均衡器优化的系统和方法
公开(公告)号：US07948699B2
公开(公告)日：2011-05-24
申请号：US12348236
申请日：2009-01-02
申请人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
发明人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10055 , G11B20/10481 , G11B20/18 , G11B2020/183 , G11B2220/2516
摘要： Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
摘要翻译：本发明的各种实施例提供了包括多路复用器，存储器缓冲器，数据处理电路和通道设置修改电路的数据处理电路。多路复用器的第一输入接收输入数据集，多路复用器的第二输入接收缓冲数据集。复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。存储器缓冲器接收多路复用器输出并提供缓冲数据集。数据处理电路的操作至少部分由通道设置决定。数据处理电路接收复用器输出并执行数据检测处理。当数据检测过程失败时，选择信号被置位以选择缓冲数据集，当数据检测过程成功时，选择信号选择输入数据集。当数据检测处理失败时，通道设置修改电路可操作以修改通道设置。

9. 发明授权

US07924523B2 Frequency domain approach for efficient computation of fixed-point equalization targets 有权
标题翻译：用于有效计算定点均衡目标的频域方法
公开(公告)号：US07924523B2
公开(公告)日：2011-04-12
申请号：US12273265
申请日：2008-11-18
申请人： George Mathew , Yuan Xing Lee , Hongwei Song , Richard Rauschmayer
发明人： George Mathew , Yuan Xing Lee , Hongwei Song , Richard Rauschmayer
IPC分类号： G11B5/035
CPC分类号： G11B20/10212 , G11B20/10046 , G11B20/10194 , G11B20/24 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for equalizing an input signal. For example, various embodiments of the present invention provide a method for performing equalization in a storage device. Such methods include providing an equalizer circuit that is governed by a target value, and a filter circuit that is governed by a filter coefficient. An initial value is provided to the equalizer circuit as the target value, and an overall target based at least in part on the initial value and the filter coefficient is calculated. An updated value is calculated based on the overall target, and the updated value is provided to the equalizer circuit as the target value.
摘要翻译：本发明的各种实施例提供了用于均衡输入信号的系统和方法。例如，本发明的各种实施例提供了一种用于在存储设备中执行均衡的方法。这样的方法包括提供由目标值控制的均衡器电路和由滤波器系数控制的滤波器电路。将初始值作为目标值提供给均衡器电路，并且至少部分地基于初始值和滤波器系数来计算总体目标。基于总体目标计算更新的值，并且将更新的值作为目标值提供给均衡器电路。

10. 发明申请

US20100172046A1 Systems and Methods for Equalizer Optimization in a Storage Access Retry 有权
标题翻译：存储访问重试中均衡器优化的系统和方法
公开(公告)号：US20100172046A1
公开(公告)日：2010-07-08
申请号：US12348236
申请日：2009-01-02
申请人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
发明人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
IPC分类号： G11B20/10
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10055 , G11B20/10481 , G11B20/18 , G11B2020/183 , G11B2220/2516
摘要： Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
摘要翻译：本发明的各种实施例提供了包括多路复用器，存储器缓冲器，数据处理电路和通道设置修改电路的数据处理电路。多路复用器的第一输入接收输入数据集，多路复用器的第二输入接收缓冲数据集。复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。存储器缓冲器接收多路复用器输出并提供缓冲数据集。数据处理电路的操作至少部分由通道设置决定。数据处理电路接收复用器输出并执行数据检测处理。当数据检测过程失败时，选择信号被置位以选择缓冲数据集，当数据检测过程成功时，选择信号选择输入数据集。当数据检测处理失败时，通道设置修改电路可操作以修改通道设置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式