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1. 发明授权

US07915662B2 Integrated memory device having columns having multiple bit lines 有权
公开(公告)号：US07915662B2
公开(公告)日：2011-03-29
申请号：US10918335
申请日：2004-08-13
申请人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
发明人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
IPC分类号： H01L29/788
摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.

2. 发明授权

US07834403B2 Bipolar transistor FINFET technology 有权
标题翻译：双极晶体管FINFET技术
公开(公告)号：US07834403B2
公开(公告)日：2010-11-16
申请号：US11837972
申请日：2007-08-13
申请人： Ronald Kakoschke , Klaus Schrüfer
发明人： Ronald Kakoschke , Klaus Schrüfer
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/8249 , H01L21/84 , H01L27/0623 , H01L27/1203 , H01L29/66265 , H01L29/7317 , H01L29/785
摘要： This document discusses, among other things, apparatus having at least one CMOS transistor overlying a substrate; and at least one finned bipolar transistor overlying the substrate and methods for making the apparatus.
摘要翻译：本文件尤其讨论了具有覆盖衬底的至少一个CMOS晶体管的器件; 以及覆盖衬底的至少一个鳍式双极晶体管和用于制造该器件的方法。

3. 发明授权

US08288813B2 Integrated memory device having columns having multiple bit lines 有权
标题翻译：具有多列位线的集成存储器件
公开(公告)号：US08288813B2
公开(公告)日：2012-10-16
申请号：US10918335
申请日：2004-08-13
申请人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
发明人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
IPC分类号： H01L29/788
CPC分类号： G11C16/0416 , H01L27/115 , H01L29/8616
摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.
摘要翻译：提出了使用隧道场效应晶体管（TFET）和掩埋位线的存储器件。存储器件包括包含存储单元的行和列的矩阵。每个存储单元包含至少一个单元晶体管，其又包含第一掺杂区域和第二掺杂区域，其中一个是源极，另一个是漏极区域。存储器件包括字线，每条字线连接到一行的存储单元和位线，每一行连接到一列的存储单元。第一掺杂区域具有与第二掺杂区域不同的掺杂类型。

4. 发明申请

US20110171803A1 INTEGRATED MEMORY DEVICE HAVING COLUMNS HAVING MULTIPLE BIT LINES 有权
标题翻译：具有多个位线的列的集成存储器件
公开(公告)号：US20110171803A1
公开(公告)日：2011-07-14
申请号：US13052728
申请日：2011-03-21
申请人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
发明人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
IPC分类号： H01L21/336
CPC分类号： G11C16/0416 , H01L27/115 , H01L29/8616
摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.
摘要翻译：提出了使用隧道场效应晶体管（TFET）和掩埋位线的存储器件。存储器件包括包含存储单元的行和列的矩阵。每个存储单元包含至少一个单元晶体管，其又包含第一掺杂区域和第二掺杂区域，其中一个是源极，另一个是漏极区域。存储器件包括字线，每条字线连接到一行的存储单元和位线，每一行连接到一列的存储单元。第一掺杂区域具有与第二掺杂区域不同的掺杂类型。

5. 发明授权

US08389357B2 Method of fabricating a memory device having a memory array including a plurality of memory cell transistors arranged in rows and columns 有权
标题翻译：一种具有存储阵列的存储器件的制造方法，所述存储器阵列包括以行和列排列的多个存储单元晶体管
公开(公告)号：US08389357B2
公开(公告)日：2013-03-05
申请号：US13052728
申请日：2011-03-21
申请人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
发明人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
IPC分类号： H01L21/336
CPC分类号： G11C16/0416 , H01L27/115 , H01L29/8616
摘要： A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line.
摘要翻译：一种在半导体衬底中制造存储器件的方法，该器件具有存储器阵列，该存储器阵列具有排列成行和列的多个存储单元晶体管。该方法包括形成多个隧穿场效应晶体管，形成第二掺杂类型的第一阱，形成围绕第一阱的第一掺杂类型的第二阱，形成连接到第一行存储单元晶体管的第一字线形成第一位线，以控制第一列存储单元晶体管的隧穿场效应晶体管的掺杂漏极区的电压，以及形成与第一位线平行的第二位线。

6. 发明授权

US08039904B2 Apparatus of memory array using finfets 有权
标题翻译：使用finfets的存储器阵列的装置
公开(公告)号：US08039904B2
公开(公告)日：2011-10-18
申请号：US12784526
申请日：2010-05-21
申请人： Ronald Kakoschke , Klaus Schruefer
发明人： Ronald Kakoschke , Klaus Schruefer
IPC分类号： H01L21/021
CPC分类号： H01L27/1052 , H01L21/84 , H01L27/115 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L29/41791 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/141
摘要： A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.
摘要翻译：存储单元包括FinFET选择装置和存储元件。在一些实施例中，存储器单元具有耦合在鳍片的表面和存储元件之间的接触元件。

7. 发明授权

US07978504B2 Floating gate device with graphite floating gate 有权
标题翻译：带石墨浮动门的浮闸装置
公开(公告)号：US07978504B2
公开(公告)日：2011-07-12
申请号：US12131938
申请日：2008-06-03
申请人： Ronald Kakoschke , Harald Seidl
发明人： Ronald Kakoschke , Harald Seidl
IPC分类号： G11C11/00
CPC分类号： H01L21/28282 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/4966
摘要： One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon allotrope.
摘要翻译：一个或多个实施例涉及一种存储器件，包括：衬底; 设置在所述基板上的电荷存储层; 以及设置在所述电荷存储层上的控制栅极，其中所述电荷存储层或所述控制栅极层包含碳同素异形体。

8. 发明申请

US20100317162A1 METHOD FOR PRODUCING AN INTEGRATED FIELD-EFFECT TRANSISTOR 有权
标题翻译：用于生成集成场效应晶体管的方法
公开(公告)号：US20100317162A1
公开(公告)日：2010-12-16
申请号：US12848576
申请日：2010-08-02
申请人： Ronald Kakoschke
发明人： Ronald Kakoschke
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/115 , H01L27/1203 , H01L29/7855 , H01L29/78612
摘要： A method for fabricating a field-effect transistor is provided. The method includes forming a substrate region, forming two terminal regions at the substrate region, one terminal region being a source region and the other terminal region being a drain region, forming two electrically insulating insulating layers, which are arranged at mutually opposite sides of the substrate region and are adjoined by control regions, forming an electrically conductive connecting region, which electrically conductively connects one of the terminal regions and the substrate region the conductive connecting region comprising a metal-semiconductor compound, leveling a surface by chemical mechanical polishing after forming the control regions, etching-back the control regions after polishing, and performing a self-aligning method for forming the metal-semiconductor compound in the etched-back regions, on the substrate region, and on a terminal region.
摘要翻译：提供了一种用于制造场效应晶体管的方法。该方法包括形成衬底区域，在衬底区域形成两个端子区域，一个端子区域是源极区域，另一个端子区域是漏极区域，形成两个电绝缘绝缘层，它们布置在并且与控制区域相邻，形成导电连接区域，该导电连接区域将导电连接区域和基板区域导电地连接到包含金属 - 半导体化合物的导电连接区域，在形成之后通过化学机械抛光来平整表面控制区域，在抛光之后蚀刻回控制区域，并且在蚀刻后区域，基板区域和端子区域上进行用于形成金属 - 半导体化合物的自对准方法。

9. 发明申请

US20100142266A1 VERTICAL FIELD-EFFECT TRANSISTOR 有权
标题翻译：垂直场效应晶体管
公开(公告)号：US20100142266A1
公开(公告)日：2010-06-10
申请号：US12704287
申请日：2010-02-11
申请人： Ronald Kakoschke , Helmut Tews
发明人： Ronald Kakoschke , Helmut Tews
IPC分类号： G11C16/04 , H01L21/336 , G11C11/34
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L29/66666 , H01L29/7827
摘要： A method produces a vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.
摘要翻译：一种方法产生具有半导体层的垂直场效应晶体管，其中掺杂沟道区沿着凹陷布置。 “埋入”端子区域导通至半导体层的表面。场效应晶体管还具有靠近凹陷的开口的掺杂端子区域以及远离开口的掺杂端子区域，布置在凹陷中的控制区域以及控制区域和沟道区域之间的电绝缘区域。远离开口的端子区域引出至包含开口的表面，或者导电地连接到通向该表面的导电连接。控制区域仅布置在一个凹部中。场效应晶体管是位于存储单元阵列的字线或位线处的驱动晶体管。

10. 发明申请

US20100129972A1 BIT LINE STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF 有权
标题翻译：位线结构及其生产方法
公开(公告)号：US20100129972A1
公开(公告)日：2010-05-27
申请号：US12695277
申请日：2010-01-28
申请人： Ronald Kakoschke , Franz Schuler , Georg Tempel
发明人： Ronald Kakoschke , Franz Schuler , Georg Tempel
IPC分类号： H01L21/762 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.
摘要翻译：为半导体元件或电路布置提供了位线结构和相关联的制造方法。位线结构包含表面位线和掩埋位线。掩埋位线形成在沟槽的上部，并且经由第一连接层连接到相关联的第一掺杂区域。通过第二沟槽绝缘层与掩埋位线绝缘的第一沟槽填充层位于沟槽的下部。

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