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1. 发明授权

US10008511B2 Dense arrays and charge storage devices 有权
公开(公告)号：US10008511B2
公开(公告)日：2018-06-26
申请号：US15368396
申请日：2016-12-02
申请人： SANDISK TECHNOLOGIES LLC
发明人： Thomas H. Lee
IPC分类号： H01L27/11582 , G11C16/34 , H01L21/822 , H01L27/06 , H01L27/112 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L29/423 , H01L29/66 , H01L29/788 , H01L29/792 , H01L29/861 , H01L27/11558 , H01L27/11526 , H01L27/11573 , H01L29/16 , G11C16/10 , G11C16/14 , G11C16/26 , H01L29/06 , H01L29/51 , G11C16/04 , H01L21/3105 , H01L21/768 , H01L23/528 , H01L23/532 , H01L27/11565 , H01L29/739 , H01L29/786 , H01L27/12 , H01L27/1158
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

2. 发明授权

US09397089B2 Group III-V HEMT having a selectably floating substrate 有权
标题翻译：具有可选择浮动衬底的III-V族HEMT组
公开(公告)号：US09397089B2
公开(公告)日：2016-07-19
申请号：US14728206
申请日：2015-06-02
申请人： International Rectifier Corporation
发明人： Yang Pan , Mohamed Imam
IPC分类号： H01L27/02 , H01L27/06 , H01L29/20 , H01L23/538 , H01L29/778 , H01L29/861 , H01L21/768 , H01L29/10 , H01L29/267
CPC分类号： H01L27/027 , H01L21/76898 , H01L21/8258 , H01L23/481 , H01L27/0248 , H01L27/0266 , H01L27/0617 , H01L27/0629 , H01L27/0694 , H01L27/0727 , H01L27/085 , H01L29/1075 , H01L29/2003 , H01L29/267 , H01L29/66666 , H01L29/7786 , H01L29/7827 , H01L29/8611 , H01L29/8616 , H01L2924/0002 , H03K17/063 , H03K17/6871 , H03K2017/6875 , H03K2217/0018 , H01L2924/00
摘要： There are disclosed herein various implementations of a group III-V high electron mobility transistor (HEMT) having a selectably floating substrate. Such a group III-V HEMT is situated over a substrate, and includes a transistor configured to selectably couple the substrate to ground and to selectably decouple the substrate from ground. The transistor is configured to ground the substrate when the group III-V HEMT is in an off-state and to cause the substrate to float when the group III-V HEMT is in an on-state.
摘要翻译：这里公开了具有可选择地浮置的衬底的III-V族高电子迁移率晶体管（HEMT）的各种实现。这种组III-V HEMT位于衬底上，并且包括被配置为可选地将衬底耦合到地并且可选择地将衬底与地分离的晶体管。当III-V族HEMT处于断开状态时，晶体管被配置为对衬底进行接地，并且当III-V族HEMT处于导通状态时，使衬底浮动。

3. 发明申请

US20160079258A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 有权
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20160079258A1
公开(公告)日：2016-03-17
申请号：US14856131
申请日：2015-09-16
申请人： SANDISK 3D LLC
发明人： Thomas H. Lee
IPC分类号： H01L27/115 , G11C16/10 , G11C16/26 , H01L29/861 , H01L29/423 , H01L29/51 , H01L29/06 , H01L27/112 , G11C16/14
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包含多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续级之间的至少一个表面平坦化。

4. 发明申请

US20150044833A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 有权
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20150044833A1
公开(公告)日：2015-02-12
申请号：US14494320
申请日：2014-09-23
申请人： SANDISK 3D LLC
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Igor G. Kouznetsov , Mark G. Johnson , Paul Michael Farmwald
IPC分类号： H01L27/115 , H01L29/66 , H01L29/16
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

5. 发明申请

US20150041751A1 CUSTOMIZABLE NONLINEAR ELECTRICAL DEVICES 有权
标题翻译：可定制非线性电气设备
公开(公告)号：US20150041751A1
公开(公告)日：2015-02-12
申请号：US14385544
申请日：2012-04-26
申请人： Minxian Max Zhang , Jianhua Yang , Gilberto Medeiros Ribeiro , R. Stanley Williams
发明人： Minxian Max Zhang , Jianhua Yang , Gilberto Medeiros Ribeiro , R. Stanley Williams
IPC分类号： H01L29/24 , H01L21/02 , H01L29/861 , H01L45/00 , H01L29/8605 , H01L29/92
CPC分类号： H01L29/24 , B82Y10/00 , G11C13/0007 , G11C13/003 , G11C2213/15 , G11C2213/72 , G11C2213/73 , G11C2213/74 , H01L21/02425 , H01L21/02565 , H01L21/02631 , H01L27/1021 , H01L27/2418 , H01L27/2463 , H01L29/0676 , H01L29/247 , H01L29/47 , H01L29/8605 , H01L29/861 , H01L29/8616 , H01L29/872 , H01L29/92 , H01L45/00 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： In one example, a customizable nonlinear electrical device includes a first conductive layer, a second conductive layer, and a thin film metal-oxide layer sandwiched between the first conductive layer and the second conductive layer to form a first rectifying interface between the metal-oxide layer and the first conductive layer and a second rectifying interface between the metal-oxide layer and the second conductive layer. The metal-oxide layer includes an electrically conductive mixture of co-existing metal and metal oxides. A method forming a nonlinear electrical device is also provided.
摘要翻译：在一个示例中，可定制的非线性电气装置包括第一导电层，第二导电层和夹在第一导电层和第二导电层之间的薄膜金属氧化物层，以在金属氧化物之间形成第一整流界面层和第一导电层以及金属氧化物层和第二导电层之间的第二整流界面。金属氧化物层包括共存的金属和金属氧化物的导电混合物。还提供了形成非线性电气装置的方法。

6. 发明授权

US08526242B2 Flash memory and fabrication method and operation method for the same 有权
标题翻译：闪存及其制作方法及操作方法相同
公开(公告)号：US08526242B2
公开(公告)日：2013-09-03
申请号：US13321120
申请日：2011-03-07
申请人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
发明人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
IPC分类号： G11C11/34
CPC分类号： H01L27/11556 , H01L29/7391 , H01L29/7889 , H01L29/8616
摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.
摘要翻译：本发明公开了一种闪存及其制作方法及其操作方法。闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

7. 发明授权

US08288813B2 Integrated memory device having columns having multiple bit lines 有权
标题翻译：具有多列位线的集成存储器件
公开(公告)号：US08288813B2
公开(公告)日：2012-10-16
申请号：US10918335
申请日：2004-08-13
申请人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
发明人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
IPC分类号： H01L29/788
CPC分类号： G11C16/0416 , H01L27/115 , H01L29/8616
摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.
摘要翻译：提出了使用隧道场效应晶体管（TFET）和掩埋位线的存储器件。存储器件包括包含存储单元的行和列的矩阵。每个存储单元包含至少一个单元晶体管，其又包含第一掺杂区域和第二掺杂区域，其中一个是源极，另一个是漏极区域。存储器件包括字线，每条字线连接到一行的存储单元和位线，每一行连接到一列的存储单元。第一掺杂区域具有与第二掺杂区域不同的掺杂类型。

8. 发明申请

US20120241829A1 Low Leakage Capacitor for Analog Floating-Gate Integrated Circuits 有权
标题翻译：用于模拟浮栅集成电路的低漏电容
公开(公告)号：US20120241829A1
公开(公告)日：2012-09-27
申请号：US13070222
申请日：2011-03-23
申请人： Imran Mahmood Khan , Allan T. Mitchell , Kaiping Liu
发明人： Imran Mahmood Khan , Allan T. Mitchell , Kaiping Liu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/94 , G11C27/005 , G11C2216/10 , H01L27/1156 , H01L27/11803 , H01L28/40 , H01L28/60 , H01L29/7883 , H01L29/8616
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
摘要翻译：集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

9. 发明申请

US20120223380A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 有权
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20120223380A1
公开(公告)日：2012-09-06
申请号：US13468731
申请日：2012-05-10
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/788 , H01L21/336 , H01L29/792
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

10. 发明申请

US20110171803A1 INTEGRATED MEMORY DEVICE HAVING COLUMNS HAVING MULTIPLE BIT LINES 有权
标题翻译：具有多个位线的列的集成存储器件
公开(公告)号：US20110171803A1
公开(公告)日：2011-07-14
申请号：US13052728
申请日：2011-03-21
申请人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
发明人： Ronald Kakoschke , Thomas Nirschl , Danny Shum , Klaus Schrüfer
IPC分类号： H01L21/336
CPC分类号： G11C16/0416 , H01L27/115 , H01L29/8616
摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.
摘要翻译：提出了使用隧道场效应晶体管（TFET）和掩埋位线的存储器件。存储器件包括包含存储单元的行和列的矩阵。每个存储单元包含至少一个单元晶体管，其又包含第一掺杂区域和第二掺杂区域，其中一个是源极，另一个是漏极区域。存储器件包括字线，每条字线连接到一行的存储单元和位线，每一行连接到一列的存储单元。第一掺杂区域具有与第二掺杂区域不同的掺杂类型。

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