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1. 发明申请

US20170227995A1 METHOD AND SYSTEM FOR IMPLICIT AUTHENTICATION 审中-公开
公开(公告)号：US20170227995A1
公开(公告)日：2017-08-10
申请号：US15428306
申请日：2017-02-09
申请人： Ruby B. Lee , Wei-Han Lee
发明人： Ruby B. Lee , Wei-Han Lee
IPC分类号： G06F1/16 , G06F3/0488 , H04L29/06 , G06F21/32 , H04W12/12 , H04W12/06 , G06F3/01 , G06F21/31
CPC分类号： G06F1/1694 , G06F1/163 , G06F1/1684 , G06F3/017 , G06F21/316 , G06F21/32 , G06F2200/1637 , G06F2221/2139 , G06N20/10 , H04L63/0861 , H04L63/0892 , H04W12/00504 , H04W12/00508 , H04W12/06 , H04W12/12
摘要： A method and system capable of implicitly authenticating users based on information gathered from one or more sensors, which may be located in one or more devices, and an authentication model trained via a machine learning technique. Data is collected, manipulated, and assessed with the authentication model in order to determine if the user is authentic. A wide variety of sensors may be utilized, including sensors in smartphones, smartwatches, other wearable devices, and other sensors accessible via an internet of things (IoT) system. The method and system can include continuously testing the user's behavior patterns and environment characteristics, and allowing authentication without interrupting the user's other interactions with a given device or requiring explicit user input. The method and system may also involve the authentication model being retrained, or adaptively updated to include temporal changes in the user's patterns.

2. 发明申请

US20100281273A1 System and Method for Processor-Based Security 有权
标题翻译：基于处理器的安全性的系统和方法
公开(公告)号：US20100281273A1
公开(公告)日：2010-11-04
申请号：US12689674
申请日：2010-01-19
申请人： Ruby B. Lee , David Champagne
发明人： Ruby B. Lee , David Champagne
IPC分类号： G06F12/14 , G06F21/22
CPC分类号： F04B33/00 , G06F21/57 , G06F21/575 , G06F21/72
摘要： A system and method for processor-based security is provided, for on-chip security and trusted computing services for software applications. A processor is provided having a processor core, a cache memory, a plurality of registers for storing at least one hash value and at least one encryption key, a memory interface, and at least one on-chip instruction for creating a secure memory area in a memory external to the processor, and a hypervisor program executed by the processor. The hypervisor program instructs the processor to execute the at least one on-chip instruction to create a secure memory area for a software area for a software module, and the processor encrypts data written to, and decrypts data read from, the external memory using the at least one encryption key and the verifying data read from the external memory using the at least one hash value. Secure module interactions are provided, as well as the generation of a power-on key which can be used to protect memory in the event of a re-boot event. Lightweight, run-time attestation reports are generated which include selected information about software modules executed by the processors, for use in determining whether the processor is trusted to provide secure services.
摘要翻译：提供了一种用于基于处理器的安全性的系统和方法，用于软件应用的片上安全和可信计算服务。提供一种处理器，其具有处理器核心，高速缓存存储器，用于存储至少一个散列值的多个寄存器和至少一个加密密钥，存储器接口以及用于创建安全存储器区域的至少一个片上指令处理器外部的存储器和由处理器执行的管理程序程序。管理程序指令处理器执行至少一个片上指令以为软件模块的软件区域创建安全存储区域，并且处理器使用以下方式对写入的数据和从外部存储器读取的数据进行加密至少一个加密密钥和使用所述至少一个哈希值从外部存储器读取的验证数据。提供安全模块交互，以及生成可以在重新启动事件的情况下保护内存的开机密钥。生成轻量级的运行时证明报告，其中包括有关由处理器执行的软件模块的选定信息，用于确定处理器是否被信任以提供安全服务。

3. 发明申请

US20100228939A1 Parallel Read Functional Unit for Microprocessors 有权
标题翻译：微处理器并行读功能单元
公开(公告)号：US20100228939A1
公开(公告)日：2010-09-09
申请号：US12690040
申请日：2010-01-19
申请人： Ruby B. Lee , Yu-Yuan Chen
发明人： Ruby B. Lee , Yu-Yuan Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F21/72 , H04L9/0631 , H04L2209/04 , H04L2209/12
摘要： A functional unit for a microprocessor is provided, which allows for fast, parallel data read, write, and manipulation operations in the microprocessor that are useful for a number of software applications, such as cryptography. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, first and second banks of memory tables, a combinational logic circuit, and a decoder. The first and second banks of memory tables are in communication with the first source register, and each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. Each index points to a lookup result in a respective one of the memory tables. The combinational logic circuit is in communication with the first and second banks of memory tables and the second source register, receives the lookup results, and processes the lookup results and the second data item in the second source register to produce a result data item. The decoder circuit is in communication with the combinational logic circuit, and extracts an operational code from an instruction supplied to the functional unit, decodes the operational code, and controls the combinational logic circuit in accordance with the operational code.
摘要翻译：提供了一种用于微处理器的功能单元，其允许在微处理器中的快速，并行数据读取，写入和操作操作，其对于诸如密码学的许多软件应用是有用的。功能单元包括用于接收要由功能单元处理的第一和第二数据项的第一和第二源寄存器，存储器表的第一和第二组，组合逻辑电路和解码器。第一和第二存储表组与第一源寄存器通信，并且每个表由包括由第一源寄存器接收的第一数据项的一部分的索引索引。每个索引指向相应的一个存储器表中的查找结果。组合逻辑电路与第一和第二组存储器表和第二源寄存器通信，接收查找结果，并处理第二源寄存器中的查找结果和第二数据项以产生结果数据项。解码器电路与组合逻辑电路通信，并从提供给功能单元的指令中提取操作码，解码操作码，并根据操作码控制组合逻辑电路。

4. 发明授权

US07424597B2 Variable reordering (Mux) instructions for parallel table lookups from registers 失效
标题翻译：来自寄存器的并行表查找的可变重排序（Mux）指令
公开(公告)号：US07424597B2
公开(公告)日：2008-09-09
申请号：US10403785
申请日：2003-03-31
申请人： Ruby B. Lee , Dale Morris
发明人： Ruby B. Lee , Dale Morris
IPC分类号： G06F9/312 , G06F9/315
CPC分类号： G06F9/30032 , G06F9/3004
摘要： Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an “Index” register. A direct variable Mux instruction can specify the table register and the index register as arguments, along with a result register. The instruction writes at least some of the data from the table register into the result register as specified in the index register. If the entire table cannot fit within a single register, entries can be divided between two or more table registers. An indirect variable Mux instruction can specify both a table-register-select register and a subword-location-select register. Both the direct and indirect Mux instructions can be used with entry data that is divided in accordance with significance between registers. In that case, plural Mux instructions are used with UnPack instructions that concatenate portions of the table entries.
摘要翻译：使用变量Mux指令实现并行表查找，以重新排序数据。表数据可以在“表”寄存器中表示，而所需的顺序可以在“索引”寄存器中表示。直接变量Mux指令可以指定表寄存器和索引寄存器作为参数，以及结果寄存器。该指令将表寄存器中的至少一些数据写入索引寄存器中指定的结果寄存器。如果整个表不能放在单个寄存器中，则可以在两个或多个表寄存器之间划分条目。间接变量Mux指令可以指定表寄存器选择寄存器和子字选择寄存器。直接和间接MUX指令都可以与根据寄存器之间的重要性划分的条目数据一起使用。在这种情况下，多个Mux指令用于连接表项部分的UnPack指令。

5. 发明授权

US06922472B2 Method and system for performing permutations using permutation instructions based on butterfly networks 有权
标题翻译：使用基于蝴蝶网络的置换指令进行排列的方法和系统
公开(公告)号：US06922472B2
公开(公告)日：2005-07-26
申请号：US09850237
申请日：2001-05-07
申请人： Ruby B. Lee , Xiao Yang , Manish Vachharajani
发明人： Ruby B. Lee , Xiao Yang , Manish Vachharajani
IPC分类号： H04L9/34 , H04K1/04 , H04K1/00 , H04K1/06 , H04K3/00
CPC分类号： G06F9/30032 , G06F9/30018 , G06F9/30036 , H04L9/34
摘要： The present invention provides permutation instructions which can be used in software executed in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. The permute instructions are based on a Benes network comprising two butterfly networks of the same size connected back-to-back. Intermediate sequences of bits are defined that an initial sequence of bits from a source register are transformed into. Each intermediate sequence of bits is used as input to a subsequent permutation instruction. Permutation instructions are determined for permitting the initial source sequence of bits into one or more intermediate sequence of bits until a desired sequence is obtained. The intermediate sequences of bits are determined by configuration bits. The permutation instructions form a permutation instruction sequence of at least one instruction. At most 21 gr/m permutation instructions are used in the permutation instruction sequence, where r is the number of k-bit subwords to be permuted, and m is the number of network stages executed in one instruction. The permutation instructions can be used to permute k-bit subwords packed into an n-bit word, where k can be 1, 2, . . . , or n bits, and k*r=n.
摘要翻译：本发明提供了可用于在可编程处理器中执行的用于解密密码学，多媒体和其他应用中的置换问题的软件中的置换指令。该置换指令是基于一个Benes网络，它包括两个背对背连接的相同尺寸的蝴蝶网络。定义位的中间序列，来自源寄存器的初始位序列被转换成。每个中间位数序列用作后续排列指令的输入。确定置换指令，以允许位的初始源序列到一个或多个中间比特序列，直到获得所需的序列。位的中间序列由配置位确定。置换指令形成至少一个指令的置换指令序列。在排列指令序列中使用最多21个字节/ m的置换指令，其中r是要置换的k位子字的数量，m是在一个指令中执行的网络级数。置换指令可用于置换打包成n位字的k位子词，其中k可以是1,2。。。，或n位，并且k * r = n。

6. 发明授权

US06381690B1 Processor for performing subword permutations and combinations 失效
标题翻译：用于执行子字排列和组合的处理器
公开(公告)号：US06381690B1
公开(公告)日：2002-04-30
申请号：US08509867
申请日：1995-08-01
申请人： Ruby B. Lee
发明人： Ruby B. Lee
IPC分类号： G06F9315
CPC分类号： G06F7/762 , G06F7/76 , G06F9/30032 , G06F9/30036
摘要： An apparatus for operating on the contents of an input register to generate the contents of an output register which contains a permutation, with or without repetitions, or a combination of the contents of the input register. The apparatus partitions the input register into a plurality of sub-words, each sub-word being characterized by a location in the input register and a length greater than one bit. In response to an instruction specifying a rearrangement of the input register, the present invention directs at least one of the sub-words in the input register to a location in the output register that differs from the location occupied by the sub-word in the input register. The ordering of the sub-words in the output register differ from the order obtainable by a single shift instruction. In the preferred embodiment of the present invention, the invention is implemented by modifying a conventional shifter comprising a plurality of layers of multiplexers. The modification comprises independently setting the control signals for at least one of the multiplexers in at least one of the layers.
摘要翻译：一种用于对输入寄存器的内容进行操作以产生包含有或没有重复的排列或输入寄存器的内容的组合的输出寄存器的内容的装置。该设备将输入寄存器分割为多个子字，每个子字的特征在于输入寄存器中的一个位置，长度大于一位。响应于指定输入寄存器的重排的指令，本发明将输入寄存器中的至少一个子字引导到输出寄存器中与输入中的子字占据的位置不同的位置寄存器。输出寄存器中的子字的排序与通过单个移位指令可获得的顺序不同。在本发明的优选实施例中，本发明通过修改包括多层复用器的常规移位器来实现。修改包括独立地设置至少一个层中的多路复用器中的至少一个的控制信号。

7. 发明授权

US4829424A Maximal length immediates with fixed sign position 失效
标题翻译：最大长度与固定符号位置相似
公开(公告)号：US4829424A
公开(公告)日：1989-05-09
申请号：US750576
申请日：1985-06-28
申请人： Ruby B. Lee
发明人： Ruby B. Lee
IPC分类号： G06F9/32 , G06F9/30 , G06F9/305 , G06F9/318
CPC分类号： G06F9/30167 , G06F9/30145 , Y10S707/99934
摘要： A computer instruction set is presented in accordance with the preferred embodiment of the present invention. Some instructions within the instruction set have immediate fields which are allowed to vary in length and fill up all unused bit positions in the instructions. A sign bit is in a fixed location for instructions within the instruction set. For example, the sign bit may be right justified with respect to the immediate field, that is the sign bit is put in the least significant (rightmost) bit position. This allows time-critical suboperations to proceed without waiting for the value of the sign bit to be located and decoded.
摘要翻译：根据本发明的优选实施例呈现计算机指令集。指令集中的某些指令具有允许长度变化并填充指令中的所有未使用位位置的立即字段。符号位在指令集内的指令的固定位置。例如，符号位可能相对于立即字段右对齐，即符号位置于最低有效位（最右侧）位。这允许在不等待符号位的值被定位和解码的情况下进行时间关键的子波。

8. 发明授权

US08738932B2 System and method for processor-based security 有权
标题翻译：用于基于处理器的安全性的系统和方法
公开(公告)号：US08738932B2
公开(公告)日：2014-05-27
申请号：US12689674
申请日：2010-01-19
申请人： Ruby B. Lee , Champagne David
发明人： Ruby B. Lee , Champagne David
IPC分类号： G06F21/00
CPC分类号： F04B33/00 , G06F21/57 , G06F21/575 , G06F21/72
摘要： A system and method for processor-based security is provided, for on-chip security and trusted computing services for software applications. A processor is provided having a processor core, a cache memory, a plurality of registers for storing at least one hash value and at least one encryption key, a memory interface, and at least one on-chip instruction for creating a secure memory area in a memory external to the processor, and a hypervisor program executed by the processor. The hypervisor program instructs the processor to execute the at least one on-chip instruction to create a secure memory area for a software area for a software module, and the processor encrypts data written to, and decrypts data read from, the external memory using the at least one encryption key and the verifying data read from the external memory using the at least one hash value. Secure module interactions are provided, as well as the generation of a power-on key which can be used to protect memory in the event of a re-boot event. Lightweight, run-time attestation reports are generated which include selected information about software modules executed by the processors, for use in determining whether the processor is trusted to provide secure services.
摘要翻译：提供了一种用于基于处理器的安全性的系统和方法，用于软件应用的片上安全和可信计算服务。提供一种处理器，其具有处理器核心，高速缓存存储器，用于存储至少一个散列值的多个寄存器和至少一个加密密钥，存储器接口以及用于创建安全存储器区域的至少一个片上指令处理器外部的存储器和由处理器执行的管理程序程序。管理程序指令处理器执行至少一个片上指令以为软件模块的软件区域创建安全存储区域，并且处理器使用以下方式对写入的数据和从外部存储器读取的数据进行加密至少一个加密密钥和使用所述至少一个哈希值从外部存储器读取的验证数据。提供安全模块交互，以及生成可以在重新启动事件的情况下保护内存的开机密钥。生成轻量级的运行时证明报告，其中包括有关由处理器执行的软件模块的选定信息，用于确定处理器是否被信任以提供安全服务。

9. 发明授权

US08285766B2 Microprocessor shifter circuits utilizing butterfly and inverse butterfly routing circuits, and control circuits therefor 有权
标题翻译：利用蝶形和反向蝶型布线电路的微处理器移位电路及其控制电路
公开(公告)号：US08285766B2
公开(公告)日：2012-10-09
申请号：US12126616
申请日：2008-05-23
申请人： Ruby B. Lee , Yedidya Hilewitz
发明人： Ruby B. Lee , Yedidya Hilewitz
IPC分类号： G06F5/01
CPC分类号： G06F5/01 , G06F7/762 , G06F9/30018 , G06F9/30032 , G06F9/3004
摘要： Microprocessor shifter circuits utilizing butterfly and inverse butterfly circuits, and control circuits therefor, are provided. The same shifter circuits can also perform complex bit manipulations at high speeds, including butterfly and inverse butterfly operations, parallel extract and deposit operations, group operations, mix operations, permutation operations, as well as instructions executed by existing microprocessors, including shift right, shift left, rotate, extract, deposit and multimedia mix operations. The shifter circuits can be provided in various combinations to provide microprocessor functional units which perform a plurality of bit manipulation operations.
摘要翻译：提供了利用蝶形和蝶形蝶形电路的微处理器移位器电路及其控制电路。相同的移位器电路也可以以高速执行复杂的位操作，包括蝶形和反向蝶形运算，并行提取和存储操作，组操作，混合操作，置换操作以及由现有微处理器执行的指令，包括右移，移位左，旋转，提取，存款和多媒体混合操作。移位器电路可以以各种组合提供，以提供执行多个位操作操作的微处理器功能单元。

10. 发明授权

US07730292B2 Parallel subword instructions for directing results to selected subword locations of data processor result register 失效
标题翻译：用于将结果指向数据处理器结果寄存器的选定子字位置的并行子字指令
公开(公告)号：US07730292B2
公开(公告)日：2010-06-01
申请号：US10403977
申请日：2003-03-31
申请人： Ruby B. Lee
发明人： Ruby B. Lee
IPC分类号： G06F7/00 , G06F15/00
CPC分类号： G06F9/30021 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30109
摘要： In the context of a microprocessor and a program, the invention provides parallel subword compare instructions that store results in a selectable intra-register subword location. In a targeting approach, an instruction permits the location to be specified; alternatively, there can be plural instructions, each associated with one of the locations. In a replicating approach, plural replicas are stored in the alternative locations. In a shifting approach, the instruction moves prior results, so that the number of subsequent iterations of the instruction determines the location of a result. The invention provides for overwriting and content-preserving instructions, and for overlapping and separate locations. The invention allows results from multiple parallel subword compare operations with relatively few instructions. The invention also provides for other parallel subword instructions.
摘要翻译：在微处理器和程序的上下文中，本发明提供了将结果存储在可选择的寄存器内单词位置的并行子字比较指令。在定位方法中，指令允许指定位置; 或者，可以有多个指令，每个指令与一个位置相关联。在复制方法中，多个副本存储在替代位置。在移动方法中，指令移动先前的结果，使得指令的后续迭代的数量确定结果的位置。本发明提供重写和内容保存指令以及重叠和分开的位置。本发明允许具有相对较少指令的多个并行子字比较操作的结果。本发明还提供了其他并行子字指令。

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