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1. 发明授权

US11049810B2 Integrated circuit device and method of manufacturing the same 有权
公开(公告)号：US11049810B2
公开(公告)日：2021-06-29
申请号：US16448666
申请日：2019-06-21
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Su-Hyun Bark , Sang-Hoon Ahn , Young-Bae Kim , Hyeok-Sang Oh , Woo-Jin Lee , Hoon-Seok Seo , Sung-Jin Kang
IPC分类号： H01L23/48 , H01L23/532 , H01L29/16 , H01L21/311 , H01L21/768 , H01L23/528 , H01L23/522 , H01L29/417 , H01L27/088 , H01L29/78 , H01L23/485 , H01L21/8234
摘要： An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

2. 发明授权

US11037872B2 Semiconductor devices and methods of manufacturing the same 有权
公开(公告)号：US11037872B2
公开(公告)日：2021-06-15
申请号：US16374901
申请日：2019-04-04
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kyu-Hee Han , Jong-Min Baek , Hoon-Seok Seo , Sang-Hoon Ahn , Woo-Jin Lee
IPC分类号： H01L23/522 , H01L21/768 , H01L21/02
摘要： A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.

3. 发明申请

US20190311992A1 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20190311992A1
公开(公告)日：2019-10-10
申请号：US16448666
申请日：2019-06-21
申请人： Samsung Electronics Co., Ltd.
发明人： Su-Hyun Bark , Sang-Hoon Ahn , Young-Bae Kim , Hyeok-Sang Oh , Woo-Jin Lee , Hoon-Seok Seo , Sung-Jin Kang
IPC分类号： H01L23/532 , H01L23/522 , H01L29/16 , H01L21/768 , H01L23/528 , H01L21/311
摘要： An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

4. 发明申请

US20180261546A1 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20180261546A1
公开(公告)日：2018-09-13
申请号：US15831603
申请日：2017-12-05
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： SU-HYUN BARK , Sang-Hoon Ahn , Young-Bae Kim , Hyeok-Sang Oh , Woo-Jin Lee , Hoon-Seok Seo , Sung-Jin Kang
IPC分类号： H01L23/532 , H01L29/16 , H01L21/311 , H01L21/768 , H01L23/528 , H01L23/522
摘要： An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

5. 发明授权

US09214381B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09214381B2
公开(公告)日：2015-12-15
申请号：US14165817
申请日：2014-01-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Woo-Jin Lee , Sang-Hoon Ahn , Gil-Heyun Choi , Jong-Won Hong
IPC分类号： H01L21/70 , H01L21/768 , H01L29/76 , H01L29/788 , H01L21/764
CPC分类号： H01L29/0649 , H01L21/764 , H01L21/76805 , H01L21/7682 , H01L21/76831
摘要： A semiconductor device includes a substrate, a conductive pattern, a side spacer, and an air gap. The substrate includes an interlayer insulating layer and a trench penetrating the interlayer insulating layer. The conductive pattern is disposed within the trench of the substrate. The side spacer is disposed within the trench. The side spacer covers an upper side surface of the conductive pattern. The air gap is disposed within the trench. The air gap is bounded by a sidewall of the trench, the side spacer, and a lower side surface of the conductive pattern. A level of a bottom surface of the conductive pattern is lower than a level of bottom surfaces of the side spacer.
摘要翻译：半导体器件包括衬底，导电图案，侧面间隔物和气隙。衬底包括层间绝缘层和贯穿层间绝缘层的沟槽。导电图案设置在基板的沟槽内。侧间隔件设置在沟槽内。侧隔板覆盖导电图案的上侧表面。气隙设置在沟槽内。气隙由沟槽的侧壁，侧面间隔物和导电图案的下侧表面限定。导电图案的底面的水平比侧面间隔物的底面的水平低。

6. 发明授权

US09355703B2 Devices, systems and methods with improved refresh address generation 有权
标题翻译：改善刷新地址生成的设备，系统和方法
公开(公告)号：US09355703B2
公开(公告)日：2016-05-31
申请号：US14077187
申请日：2013-11-11
申请人： Samsung Electronics Co., Ltd.
发明人： Woo-Jin Lee , Dae-Hyun Kim , Sang-Yun Kim , Jae-Sung Kim , Young-Soo Sohn
IPC分类号： G11C7/00 , G11C11/406 , G11C29/02 , G11C29/50
CPC分类号： G11C11/40611 , G11C11/40622 , G11C29/028 , G11C29/50016
摘要： A refresh address generator may include a lookup table including a first portion storing a first group of addresses associated with a first data retention time, and a second portion storing a second group of addresses associated with a second data retention time different from the first data retention time, wherein the addresses of the first portion are more frequently accessed than the addresses of the second portion to refresh the memory cells corresponding to the addresses. Systems and methods may also implement such refresh address generation.
摘要翻译：刷新地址生成器可以包括查找表，其包括存储与第一数据保留时间相关联的第一组地址的第一部分，以及存储与第二数据保留时间相关联的第二组地址的第二部分，该第二组地址与第一数据保留不同时间，其中第一部分的地址比第二部分的地址更频繁地访问以刷新对应于地址的存储单元。系统和方法也可以实现这种刷新地址生成。

7. 发明申请

US20130214843A1 BUFFER CIRCUIT FOR SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的缓冲电路
公开(公告)号：US20130214843A1
公开(公告)日：2013-08-22
申请号：US13717931
申请日：2012-12-18
申请人： Samsung Electronics Co., Ltd.
发明人： Kyung-Soo Ha , Ho-Seok Seol , Woo-Jin Lee
IPC分类号： H03K19/0185
CPC分类号： H03K19/018514
摘要： A buffer circuit is provided which is insensitive to a duty distortion regardless of the change of operation environment. The buffer circuit includes a current mode logic buffer and a differential-to-single-ended converter. The differential-to-single-ended converter receives first and second differential output signals to generate a single ended output signal and is configured so that an internal control node of the differential-to-single-ended converter is controlled in a negative feedback method to maintain a constant duty ratio of the single ended output signal regardless of the change of operation environment. According to some embodiments, a duty distortion of the single ended output signal due to the change of operation environment such as a process, a voltage, a temperature, etc. is reduced or minimized and thereby performance of the buffer circuit is improved and operation reliability is improved.
摘要翻译：提供了缓冲电路，其对于占空比失真不敏感，而与操作环境的变化无关。缓冲电路包括电流模式逻辑缓冲器和差分到单端转换器。差分到单端转换器接收第一和第二差分输出信号以产生单端输出信号，并且被配置为使得差分到单端转换器的内部控制节点以负反馈方式被控制保持单端输出信号的恒定占空比，而不管操作环境的变化。根据一些实施例，减少或最小化由于诸如处理，电压，温度等的操作环境的改变引起的单端输出信号的占空比失真，从而提高缓冲电路的性能和操作可靠性改进了

8. 发明授权

US11600569B2 Integrated circuit device and method of manufacturing the same 有权
公开(公告)号：US11600569B2
公开(公告)日：2023-03-07
申请号：US17230509
申请日：2021-04-14
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Su-Hyun Bark , Sang-Hoon Ahn , Young-Bae Kim , Hyeok-Sang Oh , Woo-Jin Lee , Hoon-Seok Seo , Sung-Jin Kang
IPC分类号： H01L23/48 , H01L23/532 , H01L29/16 , H01L21/311 , H01L21/768 , H01L23/528 , H01L23/522 , H01L29/417 , H01L27/088 , H01L29/78 , H01L23/485 , H01L21/8234
摘要： An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

9. 发明授权

US10444374B2 GNSS receiver and mobile system including the same 有权
公开(公告)号：US10444374B2
公开(公告)日：2019-10-15
申请号：US15293796
申请日：2016-10-14
申请人： Samsung Electronics Co., Ltd.
发明人： Jung-Jun Park , Woo-Jin Lee , Jae-Bum Cho
IPC分类号： G01S19/34 , H04B7/185
摘要： A GNSS receiver includes a RF unit, a baseband processing unit, a storage unit, a mode control unit and a counter unit. The RF unit receives a satellite signal from an external satellite. The baseband processing unit determines present operation environment of the GNSS receiver based on the satellite signal. The storage unit stores information received by the RF unit and information generated by the baseband processing unit. The mode control unit controls an operation mode of the GNSS receiver based on the present operation environment. The operation mode includes a normal mode and a low power mode. The counter unit counts a first number representing a number of consecutive times in which the GNSS receiver has entered the low power mode. When the GNSS receiver enters the low power mode, the mode control unit turns off at least one of the RF unit, the baseband processing unit and the storage unit based on the first number.

10. 发明授权

US10008407B2 Methods of manufacturing semiconductor devices including conductive structures 有权
公开(公告)号：US10008407B2
公开(公告)日：2018-06-26
申请号：US14955988
申请日：2015-12-01
申请人： Samsung Electronics Co., Ltd
发明人： Woo-Jin Lee , Byung-Hee Kim , Sang-Hoon Ahn , Woo-Kyung You , Jong-Min Baek , Nae-In Lee
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76807 , H01L21/76816 , H01L21/76849 , H01L21/76885 , H01L23/5222 , H01L23/53295 , H01L2221/1047
摘要： A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

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