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1. 发明授权

US11211102B2 Method and memory system for optimizing on-die termination settings of multi-ranks in a multi-rank memory device 有权
公开(公告)号：US11211102B2
公开(公告)日：2021-12-28
申请号：US17104114
申请日：2020-11-25
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dae-Sik Moon , Kyung-Soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
IPC分类号： G11C7/10 , G11C7/22
摘要： A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

2. 发明授权

US09685218B2 Memory device and memory system having the same 有权
公开(公告)号：US09685218B2
公开(公告)日：2017-06-20
申请号：US15236895
申请日：2016-08-15
申请人： Samsung Electronics Co., Ltd.
发明人： Young-Soo Sohn , Chul-Woo Park , Si-Hong Kim , Kwang-Il Park , Jae-Youn Youn
IPC分类号： G11C7/10 , G11C11/406 , G11C11/4076 , G11C11/408
CPC分类号： G11C11/406 , G11C11/4076 , G11C11/4087
摘要： A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

3. 发明授权

US09536586B2 Memory device and memory system having the same 有权
标题翻译：存储器件和存储器系统具有相同的功能
公开(公告)号：US09536586B2
公开(公告)日：2017-01-03
申请号：US14514416
申请日：2014-10-15
申请人： Samsung Electronics Co., Ltd.
发明人： Young-Soo Sohn , Chul-Woo Park , Si-Hong Kim , Kwang-Il Park , Jae-Youn Youn
IPC分类号： G11C7/10 , G11C11/406 , G11C11/408 , G11C11/4076
CPC分类号： G11C11/406 , G11C11/4076 , G11C11/4087
摘要： A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.
摘要翻译：存储器件包括存储单元阵列，集中访问的行检测电路和刷新控制电路。存储单元阵列包括多个存储单元行。集中访问的行检测电路基于多个存储单元行中的每一个的累积访问时间，生成指示多个存储单元行中的集中访问的存储单元行的集中访问的行地址。当从集中访问的行检测单元接收到集中访问的行地址时，刷新控制单元优先刷新与由强行访问的行地址指示的集中访问的存储单元行相邻的相邻存储单元行。存储器件有效地降低了数据丢失率。

4. 发明授权

US09461656B2 Injection-locked phase locked loop circuits using delay locked loops 有权
标题翻译：使用延迟锁定环的注入锁相环路电路
公开(公告)号：US09461656B2
公开(公告)日：2016-10-04
申请号：US14558072
申请日：2014-12-02
申请人： Samsung Electronics Co., Ltd.
发明人： Hye-Yoon Joo , Seung-Jun Bae , Young-Soo Sohn , Ho-Sung Song , Jeong-Don Ihm
IPC分类号： H03L7/06 , H03L7/087 , H03L7/07 , H03L7/083 , H03L7/099 , G11C7/22
CPC分类号： H03L7/087 , G11C7/222 , H03L7/07 , H03L7/083 , H03L7/0995
摘要： An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.
摘要翻译：注射锁相环（ILPLL）电路包括延迟锁定环（DLL）和ILPLL。 DLL被配置为通过对参考时钟执行延迟锁定操作来生成DLL时钟。 ILPLL包括压控振荡器（VCO），并且被配置为通过对参考时钟执行注入同步锁相操作来产生输出时钟。将DLL时钟作为VCO的注入时钟注入到VCO中。

5. 发明授权

US09318168B2 Memory system for continuously mapping addresses of a memory module having defective locations 有权
标题翻译：用于连续映射具有缺陷位置的存储器模块的地址的存储器系统
公开(公告)号：US09318168B2
公开(公告)日：2016-04-19
申请号：US14090510
申请日：2013-11-26
申请人： Samsung Electronics Co., Ltd.
发明人： Chul-Woo Park , Dong-Soo Kang , Su-A Kim , Jun-hee Yoo , Hak-Soo Yu , Jae-Youn Youn , Sung-hyun Lee , Kyoung-Heon Jeong , Hyo-Jin Choi , Young-Soo Sohn
IPC分类号： G06F12/02 , G11C7/10 , G11C29/00
CPC分类号： G11C7/1072 , G06F12/0223 , G06F12/0292 , G11C29/76 , G11C29/84
摘要： In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.
摘要翻译：在一个示例性实施例中，存储器系统包括存储器模块和存储器控制器。配置存储器模块基于存储器模块的不良页面的数量生成存储器模块的密度信息，坏页面是具有故障的页面。存储器控制器被配置为基于从存储器模块接收的密度信息将连续的物理地址映射到存储器模块的动态随机存取存储器（显存）地址。

6. 发明授权

US11062744B2 Memory device performing ZQ calibration, memory system, and operation method of memory device 有权
公开(公告)号：US11062744B2
公开(公告)日：2021-07-13
申请号：US16262250
申请日：2019-01-30
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Donghun Lee , Daesik Moon , Young-Soo Sohn , Young-Hoon Son , Ki-Seok Oh , Changkyo Lee , Hyun-Yoon Cho , Kyung-Soo Ha , Seokhun Hyun
IPC分类号： G11C7/10 , G06F3/06
摘要： A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

7. 发明申请

US20190304517A1 METHOD AND MEMORY SYSTEM FOR OPTIMIZING ON-DIE TERMINATION SETTINGS OF MULTI-RANKS IN A MULTI-RANK MEMORY DEVICE 审中-公开
公开(公告)号：US20190304517A1
公开(公告)日：2019-10-03
申请号：US16363077
申请日：2019-03-25
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dae-Sik Moon , Kyung-soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
IPC分类号： G11C7/10 , G11C7/22
摘要： A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

8. 发明授权

US09552867B2 Semiconductor memory devices and memory systems including the same 有权
标题翻译：半导体存储器件和包括其的存储器系统
公开(公告)号：US09552867B2
公开(公告)日：2017-01-24
申请号：US14588496
申请日：2015-01-02
申请人： Samsung Electronics Co., Ltd.
发明人： Young-Soo Sohn , Uk-Song Kang , Kwang-Il Park , Chul-Woo Park , Hak-Soo Yu , Jae-Youn Youn
IPC分类号： G06F3/06 , G11C11/408 , G11C5/02 , G11C7/02
CPC分类号： G11C11/4087 , G11C5/025 , G11C7/02 , G11C11/4085
摘要： A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.
摘要翻译：半导体存储器件包括控制逻辑和其中布置有多个存储器单元的存储单元阵列。存储单元阵列包括多个存储体阵列，并且多个存储体阵列中的每一个包括多个子阵列。控制逻辑基于命令和地址信号控制对存储器单元阵列的访问。控制逻辑动态地设置包括在第一字线被启用时基于第一字线被去激活的多个存储器单元行的保留区。第一字线耦合到多个子阵列中的第一子阵列的第一存储单元行。因此，可以补偿增加的定时参数，并且可以增加并行性。

9. 发明授权

US09087602B2 Volatile memory device capable of relieving disturbances of adjacent memory cells and refresh method thereof 有权
标题翻译：能够缓解相邻存储单元的干扰的易失性存储器件及其刷新方法
公开(公告)号：US09087602B2
公开(公告)日：2015-07-21
申请号：US14219374
申请日：2014-03-19
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-Youn Youn , Su-A Kim , Chul-Woo Park , Young-Soo Sohn
IPC分类号： G11C7/20 , G11C11/406
CPC分类号： G11C11/40615 , G11C7/02 , G11C7/1063 , G11C11/40611 , G11C11/40618
摘要： Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal.
摘要翻译：提供了一种易失性存储器件的刷新方法。该方法包括：随着对第一存储器区域的访问次数的增加，检测影响第二存储器区域的多个干扰; 当检测到的干扰次数达到参考值时，将来自易失性存储器件的警报信号输出到易失性存储器件的外部; 以及响应于所述警报信号对所述第二存储区域执行刷新操作。

10. 发明授权

US11508420B2 Memory device, memory system, and operation method of memory device 有权
公开(公告)号：US11508420B2
公开(公告)日：2022-11-22
申请号：US17355765
申请日：2021-06-23
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Donghun Lee , Daesik Moon , Young-Soo Sohn , Young-Hoon Son , Ki-Seok Oh , Changkyo Lee , Hyun-Yoon Cho , Kyung-Soo Ha , Seokhun Hyun
IPC分类号： G11C7/10 , G06F3/06 , G11C29/02 , G11C29/50
摘要： A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

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